SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 63

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

RC5: CK Driver Characteristics Control Word
RC8: Additional IBT Setting Control Word
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
DBA1
DBA1
1
Tn inputs.
2
may be.
3
cluding DCSn and DODTn) is turned off.
x
x
x
x
0
0
1
1
x
0
1
x
x
x
x
x
x
x
If MIRROR is HIGH, then Input Bus Termination (IBT) is turned off on all inputs, except DCSn and DOD-
When DBA0 = 1, DA4 = 1, or DA3 = 1, IBT on all inputs is turned off no matter what the DBA1 setting
With this setting, no matter what the logic level of the MIRROR input pin may be, IBT on all inputs (in-
DBA0
DBA0
0
x
x
0
0
0
1
1
1
1
x
x
x
x
0
1
0
1
Input
Input
DA4
DA4
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
0
x
x
0
1
1
0
0
1
1
0
0
1
1
x
x
x
x
DA3
DA3
0
x
x
1
0
1
0
1
0
1
0
1
0
1
x
x
x
x
IBT Compatibility Settings
Clock Y1, Y1, Y3, and Y3
Clock Y0, Y0, Y2, and Y2
Input Bus Termination
Output Drivers
Output Drivers
Mirror Mode
Definition
Definition
1
Moderate Drive (8 or 10 DRAM Loads)
Moderate Drive (8 or 10 DRAM Loads)
Strong Drive (16 or 20 DRAM Loads)
Strong Drive (16 or 20 DRAM Loads)
Light Drive (4 or 5 DRAM Loads)
Light Drive (4 or 5 DRAM Loads)
IBT Off when MIRROR is HIGH
IBT On when MIRROR is HIGH
63
IBT as defined in RC2
Encoding
Encoding
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
200Ω
300Ω
Off
3
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
2
1
7314/8