SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 49

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) With RC9 DBA0=’1’.
(3) When CK/CK inputs are floated, CK/CK inputs are pulled LOW by the (10K-100K Ohm) pulldown resistor in the CK/CK
input buffer.
(4) Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input level is.
For all other operation QxCSn outputs will follow DCSn inputs.
DAn, DBAn
RESET
PAR_IN
QxCS[j,1]
QxCS[i,0]
QxODTn
QxCKEn
DCS[i,0]
DCS[j,1]
CK/CK
Yn
QxAn,
QxBAn
DRAS
DCAS
DWE
DODTn
DCKEn
QxRAS,
QxCAS,
Output
QxWE
Input
High or Low
High or Low
High or Low
High or Low
High
H or L
H or L
High or Low
n-1
High or Low
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
n-1
n
t
CKoff
n
t
QDIS
tInDIS
High
High
High
High
Clock Stopped Power Down Entry and Exit with IBT Off
n+4
n+4
t
Low
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CKEV
Hi-Z
Hi-Z
Hi-Z
L or Float*
driven Low
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Low
QxCSn and QxODTn transfer from Hi-Z to high/low with in-accurate phase
ODT8
see Note 3
t
t
ACT
STAB
see Note 3
ODT9
ODT10 ODT11
m
49
High or Low
Either or both DCKEn inputs are driven High
t
High
High
EN
tFixedoutput
p
High or Low
High or Low
Either or both QxCKEn outputs are driven High
ODT12
t
Fixedoutput
High
High
ODT13
COMMERCIAL TEMPERATURE RANGE
ODT14 ODT15
m+4
Low
SSTE32882KA1
p+4
Low
High or Low
ODT16 ODT17
qp+7
m+8
x
x
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