SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 15

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

PLL Function Table
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
RESET
1
from the PLL powerdown control and test logic. It is controlled by setting or clearing the corresponding bit in the Clock Driver
mode register.
2
HIGH) when RESET is driven HIGH.
3
H
H
H
H
H
H
H
H
H
H
H
L
The Output Enable (OEn) to disable the output buffer is not an input signal to the SSTE32882KA1, but an internal signal
It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and
This is a device test mode and all register timing parameters are not guaranteed.
VDD nominal
VDD nominal
VDD nominal
VDD nominal
VDD nominal
AV
GND
GND
GND
GND
GND
X
X
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
DD
3
3
3
3
3
Inputs
OEn
X
H
H
X
H
H
X
X
L
L
L
L
1
CK
X
H
H
H
H
H
L
L
L
L
L
L
2
CK
X
H
H
H
H
H
L
L
L
L
L
L
2
Float
Float
Float
Float
Float
Float
Float
Yn
H
H
L
L
Float
Float
Float
Float
Float
Float
Float
Yn
15
H
L
H
L
Outputs
FB
Reserved
Float
Float
Float
H
H
OUT
H
H
L
L
L
L
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
FB
Float
Float
Float
H
H
H
H
L
L
L
L
OUT
Bypassed/Off
Bypassed/Off
Bypassed/Off
Bypassed/Off
Bypassed/Off
PLL
Off
Off
On
On
On
On
7314/8