SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 28

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

AC Specifications - Output Timing Requirements
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Symbol
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
t
t
PDM
t
1
2
3
than 1.0 ns, If t
4
DIS
EN
See “Qn and Yn Load Circuit” diagram.
See “Propagation Delay Timing” diagram below.
t
See “Voltage Waveforms Address Floating” diagram
PDM
Propagation delay,
single-bit switching
(1.5V operation)
Propagation delay,
single-bit switching
(1.35V operation)
Output disable time
(1/2-Clock pre-launch)
Output disable time
(3/4-Clock pre-launch)
Output enable time
(1/2-Clock pre-launch)
Output enable time
(3/4-Clock pre-launch)
range (t
PDM_max
Parameter
PDM_max
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
for a device is 1.2 ns, it’s t
- t
3
1
PDM_min
) must remain as 350 ps. For example, if t
CK/CK to
output
Yn/Yn
(falling edge)
to output
float
Yn/Yn
(falling edge)
output driving
Conditions
4
2
PDM_min
tQSK1(max)
tQSK2(max)
tQSK1(min)
tQSK2(min)
.
-800/ 1066/1333
cannot be less than 0.85 ns.
DDR3/DDR3L
0.25+
0.75-
Min
0.5+
0.65
0.65
0.5-
Max
1.0
1.2
PDM_min
tQSK1(max)
tQSK2(max)
tQSK1(min)
tQSK2(min)
DDR3/DDR3L
for a device is 0.65 ns, it’s t
0.25+
0.75-
Min
0.5+
0.65
0.65
0.5-
28
-1600
Max
1.0
1.2
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
tQSK1(max)
tQSK2(max)
tQSK1(min)
tQSK2(min)
0.25+
PDM_max
0.75-
Min
0.65
0.5+
0.5-
DDR3-1866
cannot be more
Max
1.0
7314/8
Unit
ns
ps
ps