SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 4

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

Block Diagram - Parity Logic Diagram (Positive Logic)
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
1 DCS[n:0] indicates all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0]
indicates all of the chip select outputs.
DA0..DA15,
DBA0..DBA2,
DRAS, DCAS,
DWE
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
FBIN
FBIN
DODT0,
DODT1
PAR_IN
DCKE0,
DCKE1
V
DCS[n:0]
RESET
CK
CK
REF
(1)
10KΩ - 100KΩ
CS Logic
DRAS
DCAS
DWE
PLL
D
R
D
R
D
R
D
R
D
R
CE
CE
Q
Q
Q
Q
Q
Parity Generator
Error Check
and
Output Inversion Disabled
3T Timing Enabled
Internal Logic
Internal Logic
Internal Logic
Internal Logic
Internal Logic
4
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
FBOUT
FBOUT
QA0..QA15,
QBA0..QBA2,
QRAS, QCAS,
QWE
ERROUT
QxCS[n:0]
QACKEn
QBCKEn
QAODTn
QBODTn
(1)
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