SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 46

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
QxCS[j,1]
DCS[i,0]
QxCS[i,0]
CK
RESET
DAn,DBAn
DRAS,
DCAS,
DWE
PAR_IN
DODTn
DCKEn
DCS[j,1]
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Yn
QxAn,
QxBAn
QxRAS,
QxCAS,
QxWE
QxODTn
QxCKEn
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force SSTE32882KA1 into Register
Control Word access mode.
(3) UPon CKE Power Down exit, QxCSn will be held HIGH for a maximum of 1 tCK regardless of what DCSn input level is. For all other
operation, QxCSn outputs will follow DCSn inputs.
To re-enable the SSTE32882KA1 from this Power Down Mode with IBT on, valid logic levels are required at all device inputs
when either or both DCKEn inputs are driven High. Upon either DCKE0 or DCKE1 input going High, the SSTE32882KA1
immediately starts driving High on the appropriate QxCKEn signals. The QxCSn signals are driven high and the QxODTn
signals follow the inputs. Other output signals QxRAS, QxCAS, QxWE and QxAddr are driven either high or low to ensure
stable valid logic on all device outputs when QxCKEn goes High. The device drives output signals to these levels for
t
corresponding input levels. When exiting CKE power down mode, either one of the Chip Select register inputs DCSn can be
asserted for 1 tCK. For QuadCS capable register, when working in quad rank mode, either two of the Chip Select register
inputs DCSn can be asserted for 1 tCK. The device guarantees that input receivers are stablized within t
after DCKEn input is driven High. This is shown in the previous diagram.
FIXEDOUTPUT
H or L
High or Low
High or Low
High or Low
High or Low
n-1
H or L
n-1
n
n
t
QDIS
H, L or Hi-Z
H, L or Hi-Z
H, L or Hi-Z
tInDIS
High
High
High
High
to allow input receivers to be stablized. After the input receivers are stablized, the register output follow their
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
n+4
n+4
Output buffers are Hi-z
High
Low
Hi-z
Hi-z
Hi-z
Hi-z
High, Low or Toggling
Follows Input (High, Low or Toggling)
Power Down Mode Entry and Exit with IBT On
Hi-z
Low
Hi-z
Hi-z
Hi-z
Hi-z
n+8
n+8
see Note 3
see Note 3
H or L
n+12
H or L
tFixedoutput
t
EN
H, L or Hi-Z
H, L or Hi-Z
H, L or Hi-Z
n+12
tFixedoutput
High or Low
High or Low
Either or both DCKEn inputs are driven High
High
High
Either or both QxCKEn outputs are driven High
High
High
n+16
n+16
46
Follows Input (High or Low)
Follows Input (High or Low)
High or Low
High or Low
n+20
COMMERCIAL TEMPERATURE RANGE
n+20
SSTE32882KA1
FIXEDOUTPUT
clocks
7314/8