PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 28

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
disconnect after at least one data transfer has been completed, PI7C8150 does not initiate
any further attempts to read more data.
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If PI7C8150 is unable to obtain read data from the target after 2
(default) or 2
(maximum) attempts, PI7C8150 will report system error. The number of attempts is
programmable. PI7C8150 also asserts P_SERR_L if the primary SERR_L enable bit is set
in the command register. See Section 6.4 for information on the assertion of P_SERR_L.
Once PI7C8150 receives DEVSEL_L and TRDY_L from the target, it transfers the data
read to the opposite direction read data queue, pointing toward the opposite inter-face,
before terminating the transaction. For example, read data in response to a downstream
read transaction initiated on the primary bus is placed in the upstream read data queue. The
PI7C8150 can accept one DWORD of read data each PCI clock cycle; that is, no master
wait states are inserted. The number of DWORD’s transferred during a delayed read
transaction depends on the conditions given in Table 4-4 (assuming no disconnect is
received from the target).
3.6.6
DELAYED READ COMPLETION ON INITIATOR BUS
When the transaction has been completed on the target bus, and the delayed read data is at
the head of the read data queue, and all ordering constraints with posted write transactions
have been satisfied, the PI7C8150 transfers the data to the initiator when the initiator
repeats the transaction. For memory read transactions, PI7C8150 aliases the memory read,
memory read line, and memory read multiple bus commands when matching the bus
command of the transaction to the bus command in the delayed transaction queue.
PI7C8150 returns a target disconnect along with the transfer of the last DWORD of read
data to the initiator. If PI7C8150 initiator terminates the transaction before all read data has
been transferred, the remaining read data left in data buffers is discarded.
When the master repeats the transaction and starts transferring prefetchable read data from
data buffers while the read transaction on the target bus is still in progress and before a read
boundary is reached on the target bus, the read transaction starts operating in flow-through
mode. Because data is flowing through the data buffers from the target to the initiator, long
read bursts can then be sustained. In this case, the read transaction is allowed to continue
until the initiator terminates the transaction, or until an aligned 4KB address boundary is
reached, or until the buffer fills, whichever comes first. When the buffer empties,
PI7C8150 reflects the stalled condition to the initiator by disconnecting the initiator with
data. The initiator may retry the transaction later if data are needed. If the initiator does not
need any more data, the initiator will not continue the disconnected transaction. In this
case, PI7C8150 will start the master timeout timer. The remaining read data will be
discarded after the master timeout timer expires. To provide better latency, if there are any
other pending data for other transactions in the RDB (Read Data Buffer), the remaining
read data will be discarded even though the master timeout timer has not expired.
PI7C8150 implements a master timeout timer that starts counting when the delayed read
completion is at the head of the delayed transaction queue, and the read data is at the head
of the read data queue. The initial value of this timer is programmable through
configuration register. If the initiator does not repeat the read transaction and before the
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master timeout timer expires (2
default), PI7C8150 discards the read transaction and read
data from its queues. PI7C8150 also conditionally asserts P_SERR_L (see Section 6.4).
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March 19, 2003 – Revision 1.04