PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 58

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

6.4
SYSTEM ERROR (SERR#) REPORTING
PI7C8150 uses the P_SERR_L signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section 7.2.3.
Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the
following conditions apply:
!
!
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8150 asserts
P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the
SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8150 also
sets the received system error bit in the secondary status register.
PI7C8150 also conditionally asserts P_SERR_L for any of the following reasons:
!
!
!
!
!
!
!
The device-specific P_SERR_L status register reports the reason for the assertion of
P_SERR_L. Most of these events have additional device-specific disable bits in the
P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion
2
3
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
P_SERR#
1
1
1
1
X = don’t care
For PI7C8150 to assert P_SERR_L for any reason, the SERR_L enable bit must be set
in the command register.
Whenever PI7C8150 asserts P_SERR_L, PI7C8150 must also set the signaled system
error bit in the status register.
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
received)
Parity error reported on target bus during posted write transaction (see previous
section)
Delayed write data discarded after 2
received)
Delayed read data cannot be transferred from target after 2
target retries received)
Master timeout on delayed transaction
Transaction Type
Delayed Write
Delayed Write
Delayed Write
Delayed Write
48
Direction
Downstream
Downstream
Upstream
Upstream
24
24
(default) attempts to deliver (2
(default) attempts to deliver (2
March 19, 2003 – Revision 1.04
Primary
Secondary
Primary
Secondary
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
Was Detected
ADVANCE INFORMATION
24
(default) attempts (2
24
24
target retries
x / x
x / x
x / x
x / x
target retries
Secondary Parity
Error Response
Primary /
Bits
PI7C8150
24