PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 57

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

Table 6-6. Assertion of S_PERR#
Table 6-7. Assertion of P_SERR# for Data Parity Errors
Table 6–6 shows assertion of S_PERR_L that is set under the following conditions:
!
!
!
2
Table 6–7 shows assertion of P_SERR_L. This signal is set under the following
conditions:
!
!
!
!
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
S_PERR#
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
0
0
X = don’t care
P_SERR#
1 (de-asserted)
1
1
1
1
0
0
1
2
2
3
(asserted)
PI7C8150 is either the target of a write transaction or the initiator of a read transaction
on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
PI7C8150 detects a data parity error on the secondary bus or detects P_PERR_L
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.
PI7C8150 has detected P_PERR_L asserted on an upstream posted write transaction
or S_PERR_L asserted on a downstream posted write transaction.
PI7C8150 did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit
on the bridge control register must both be set.
The SERR_L enable bit must be set in the command register.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
47
Direction
Downstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Upstream
Downstream
Downstream
Upstream
March 19, 2003 – Revision 1.04
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
Was Detected
Was Detected
ADVANCE INFORMATION
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
x / x
1 / 1
x / 1
x / x
x / x
x / x
x / x
x / x
1 / 1
1 / 1
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary /
Primary/
Bits
Bits
PI7C8150