PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 7

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

15
16
17
18
LIST OF TABLES
Table 3-1. Pin list – 208-pin FQFP_______________________________________________________ 7
Table 3-2. Pin list – 256-ball PBGA ______________________________________________________ 9
Table 4-1. PCI Transactions ___________________________________________________________ 11
Table 4-2. Write Transaction Forwarding ________________________________________________ 12
Table 4-3. Write Transaction Disconnect Address Boundaries ________________________________ 15
Table 4-4. Read Prefetch Address Boundaries _____________________________________________ 16
15.1
15.2
16.1
16.2
16.3
16.4
16.5
16.6
17.1
17.2
17.3
17.4
17.5
17.6
18.1
18.2
18.3
14.1.43
14.1.44
14.1.45
14.1.46
14.1.47
14.1.48
14.1.49
14.1.50
14.1.51
14.1.52
14.1.53
14.1.54
14.1.55
15.2.1
15.2.2
15.2.3
15.2.4
16.1.1
16.1.2
BRIDGE BEHAVIOR.................................................................................................................... 82
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER................................................................ 83
ELECTRICAL AND TIMING SPECIFICATIONS................................................................... 90
PACKAGE INFORMATION........................................................................................................ 92
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES................................................................ 82
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)..................................... 82
BOUNDARY SCAN ARCHITECTURE ..................................................................................... 83
BOUNDARY SCAN INSTRUCTION SET ................................................................................. 85
TAP TEST DATA REGISTERS .................................................................................................. 85
BYPASS REGISTER ................................................................................................................... 86
BOUNDARY-SCAN REGISTER................................................................................................ 86
TAP CONTROLLER ................................................................................................................... 86
MAXIMUM RATINGS ............................................................................................................... 90
DC SPECIFICATIONS ................................................................................................................ 90
AC SPECIFICATIONS ................................................................................................................ 91
66MHZ TIMING .......................................................................................................................... 91
33MHZ TIMING .......................................................................................................................... 92
POWER CONSUMPTION........................................................................................................... 92
208-PIN FQFP PACKAGE DIAGRAM....................................................................................... 92
256-BALL PBGA PACKAGE DIAGRAM.................................................................................. 93
PART NUMBER ORDERING INFORMATION ........................................................................ 93
MASTER ABORT................................................................................................................ 82
PARITY AND ERROR REPORTING ................................................................................ 82
REPORTING PARITY ERRORS ....................................................................................... 83
SECONDARY IDSEL MAPPING ...................................................................................... 83
TAP PINS ............................................................................................................................ 84
INSTRUCTION REGISTER .............................................................................................. 84
RETRY COUNTER REGISTER – OFFSET 78h .......................................................... 79
PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 79
SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h ............................... 79
CAPABILITY ID REGISTER – OFFSET B0h ............................................................. 79
NEXT POINTER REGISTER – OFFSET B0h ............................................................. 80
SLOT NUMBER REGISTER – OFFSET B0h .............................................................. 80
CHASSIS NUMBER REGISTER – OFFSET B0h ....................................................... 80
CAPABILITY ID REGISTER – OFFSET DCh............................................................. 80
NEXT ITEM POINTER REGISTER – OFFSET DCh ................................................. 80
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh ................. 80
POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 81
CAPABILITY ID REGISTER – OFFSET E4h ............................................................. 81
NEXT POINTER REGISTER – OFFSET E4h ............................................................. 81
vii
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150