PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 63

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
priority group can be serviced n transactions out of n+1, while one member of the low
priority group is serviced once every n+1 transactions. Figure 9–1 shows an example of an
internal arbiter where four masters, including PI7C8150, are in the high priority group, and
five masters are in the low priority group. Using this example, if all requests are always
asserted, the highest priority rotates among the masters in the following fashion (high
priority members are given in italics, low priority members, in boldface type): B, m0, m1,
m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7
and so on.
Figure 9-1. Secondary Arbiter Example
Each bus master, including PI7C8150, can be configured to be in either the low priority
group or the high priority group by setting the corresponding priority bit in the arbiter-
control register. The arbiter-control register is located at offset 40h. Each master has a
corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If
the bit is set to 0, the master is assigned to the low priority group. If all the masters are
assigned to one group, the algorithm defaults to a straight rotating priority among all the
masters. After reset, all external masters are assigned to the low priority group, and
PI7C8150 is assigned to the high priority group. PI7C8150 receives highest priority on the
target bus every other transaction, and priority rotates evenly among the other masters.
Priorities are re-evaluated every time S_FRAME_L is asserted at the start of each new
transaction on the secondary PCI bus. From this point until the time that the next
transaction starts, the arbiter asserts the grant signal corresponding to the highest priority
request that is asserted. If a grant for a particular request is asserted, and a higher priority
request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the
grant corresponding to the new higher priority request on the next PCI clock cycle. When
priorities are re-evaluated, the highest priority is assigned to the next highest priority
master relative to the master that initiated the previous transaction. The master that initiated
the last transaction now has the lowest priority in its group.
If PI7C8150 detects that an initiator has failed to assert S_FRAME_L after 16 cycles of
both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one
grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and
asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is
busy, that is, S_FRAME_L or S_IRDY_L is asserted, the arbiter can be de-asserted one
grant and asserted another grant during the same PCI clock cycle.
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March 19, 2003 – Revision 1.04