PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 52

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

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For downstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150 has write status to return, the following events occur:
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!
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Similarly, for upstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150 has write status to return, the following events occur:
!
!
!
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
!
!
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the following
events occur:
!
When parity error is forwarded back from the target bus
PI7C8150 first asserts P_TRDY_L and then asserts P_PERR_L two cycles later, if the
primary interface parity-error-response bit is set in the command register.
PI7C8150 sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
PI7C8150 first asserts S_TRDY_L and then asserts S_PERR_L two cycles later, if the
secondary interface parity-error-response bit is set in the bridge control register (offset
3Ch).
PI7C8150 sets the secondary interface parity-error-detected bit in the secondary status
register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
PI7C8150 asserts P_PERR_L two cycles after the data transfer, if the following are
both true:
PI7C8150 completes the transaction normally.
PI7C8150 asserts S_PERR_L two cycles after the data transfer, if the following are
both true:
!
!
!
!
The parity-error-response bit is set in the command register of the primary
interface.
The parity-error-response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
The parity error response bit is set in the bridge control register of the
secondary interface.
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March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150