PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 60

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

transactions that are a part of the locked transaction sequence are still posted. Memory read
transactions that are a part of the locked transaction sequence are not pre-fetched.
When the locked delayed memory read request is queued, PI7C8150 does not queue any
more transactions until the locked sequence is finished. PI7C8150 signals a target retry to
all transactions initiated subsequent to the locked read transaction that are intended for
targets on the other side of PI7C8150. PI7C8150 allows any transactions queued before the
locked transaction to complete before initiating the locked transaction.
When the locked delayed memory read request transaction moves to the head of the
delayed transaction queue, PI7C8150 initiates the transaction as a locked read transaction
by de-asserting LOCK_L on the target bus during the first address phase, and by asserting
LOCK_L one cycle later. If LOCK_L is already asserted (used by another initiator),
PI7C8150 waits to request access to the secondary bus until LOCK_L is de-asserted when
the target bus is idle. Note that the existing lock on the target bus could not have crossed
PI7C8150. Otherwise, the pending queued locked transaction would not have been queued.
When PI7C8150 is able to complete a data transfer with the locked read transaction, the
lock is established on the secondary bus.
When the initiator repeats the locked read transaction on the primary bus with the same
address, transaction type, and byte enable bits, PI7C8150 transfers the read data back to the
initiator, and the lock is then also established on the primary bus.
For PI7C8150 to recognize and respond to the initiator, the initiator’s subsequent attempts
of the read transaction must use the locked transaction sequence (de-assert LOCK_L during
address phase, and assert LOCK_L one cycle later). If the LOCK_L sequence is not used in
subsequent attempts, a master timeout condition may result. When a master timeout
condition occurs, SERR_L is conditionally asserted (see Section 6.4), the read data and
queued read transaction are discarded, and the LOCK_L signal is de-asserted on the target
bus.
Once the intended target has been locked, any subsequent locked transactions initiated on
the initiator bus that are forwarded by PI7C8150 are driven as locked transactions on the
target bus.
The first transaction to establish LOCK_L must be Memory Read. If the first transaction is
not Memory read, the following transactions behave accordingly:
!
!
!
!
!
When PI7C8150 receives a target abort or a master abort in response to the delayed locked
read transaction, this status is passed back to the initiator, and no locks are established on
either the target or the initiator bus. PI7C8150 resumes forwarding unlocked transactions in
both directions.
Type 0 Configuration Read/Write induces master abort
Type 1 Configuration Read/Write induces master abort
I/O Read induces master abort
I/O Write induces master abort
Memory Write induces master abort
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March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150