PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 85

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

14.1.36
14.1.37
14.1.38
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER
– OFFSET 54h
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS
REGISTER – OFFSET 58h
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h
19:16
31:20
Bit
31:0
Bit
31:0
Bit
0
1
2
3
64 bit addressing
Upstream
Memory Limit
Address
Function
Upstream
Memory Base
Address
Function
Upstream
Memory Limit
Address
Function
Reserved
Posted Write
Parity Error
Posted Write
Non-Delivery
Target Abort
During Posted
Write
R/O
R/W
Type
R/W
Type
R/W
Type
R/O
R/W
R/W
R/W
0: 32 bit addressing
1: 64 bit addressing
Reset to 1
Controls upstream memory limit address.
Reset to 000FFFFFh
Description
Defines bits [63:32] of the upstream memory base
Reset to 0
Description
Defines bits [63:32] of the upstream memory limit
Reset to 0
Description
Reserved. Returns 0 when read. Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it is unable to
transfer any read data from the target after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not assert if this event occurs.
Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it is unable to
transfer delayed write data after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150’s ability to assert P_SERR_L when it receives a
target abort when attempting to deliver posted write data.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
75
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
24
attempts.
24
attempts.
PI7C8150