PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 36

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

3.8.3.2
3.8.3.3
Table 4-8. Response to Posted Write Target Termination
After the PI7C8150 makes 2
the target bus, PI7C8150 asserts P_SERR_L if the SERR_L enable bit (bit 8
of command register for the secondary bus) is set and the delayed-write-non-delivery bit is
not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register
(offset 64h). PI7C8150 will report system error. See Section 6.4 for a description of system
error conditions.
POSTED WRITE TARGET TERMINATION RESPONSE
When PI7C8150 initiates a posted write transaction, the target termination cannot
be passed back to the initiator. Table 4–8 shows the response to each type of target
termination that occurs during a posted write transaction.
Note that when a target retry or target disconnect is returned and posted write data
associated with that transaction remains in the write buffers, PI7C8150 initiates another
write transaction to attempt to deliver the rest of the write data. If there is a target retry, the
exact same address will be driven as for the initial write trans-action attempt. If a target
disconnect is received, the address that is driven on a subsequent write transaction attempt
will be updated to reflect the address of the current DWORD. If the initial write transaction
is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the
target is performed before a target disconnect is received, PI7C8150 will use the memory
write command to deliver the rest of the write data. It is because an incomplete cache line
will be transferred in the subsequent write transaction attempt.
After the PI7C8150 makes 2
posted write data associated with that transaction, PI7C8150 asserts P_SERR_L if the
primary SERR_L enable bit is set (bit 8 of command register for secondary bus) and
posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of
P_SERR_L event disable register (offset 64h). PI7C8150 will report system error. See
Section 6.4 for a discussion of system error conditions.
DELAYED READ TARGET TERMINATION RESPONSE
When PI7C8150 initiates a delayed read transaction, the abnormal target responses can be
passed back to the initiator. Other target responses depend on how much data the initiator
requests. Table 4–9 shows the response to each type of target termination that occurs
during a delayed read transaction.
PI7C8150 repeats a delayed read transaction until one of the following conditions is met:
!
!
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
PI7C8150 completes at least one data transfer.
PI7C8150 receives a master abort.
Repsonse
No additional action.
Repeating write transaction to target.
Initiate write transaction for delivering remaining posted write data.
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
24
24
(default) write transaction attempts and fails to deliver all
(default) attempts of the same delayed write trans-action on
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March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150