NP8P128A13BSM60E Micron Technology Inc, NP8P128A13BSM60E Datasheet
NP8P128A13BSM60E
Specifications of NP8P128A13BSM60E
Related parts for NP8P128A13BSM60E
NP8P128A13BSM60E Summary of contents
Page 1
Numonyx® Omneo™ P8P PCM 128-Mbit Parallel Phase Change Memory Product Features High Performance Read — 115 ns initial read access — 135 ns initial read access — 8-word asynchronous-page read Architecture — Asymmetrically-blocked architecture — Four 32-KByte parameter ...
Page 2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR Legal Lines and Disclaimers OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS ...
Page 3
Numonyx® Omneo™ P8P Datasheet 1.0 Product Description ................................................................................................... 6 1.1 Introduction ....................................................................................................... 6 1.2 Product Overview ................................................................................................ 7 1.3 Memory Map....................................................................................................... 9 2.0 Package Information ............................................................................................... 11 2.1 56-Lead TSOP................................................................................................... 11 2.2 64-Ball Easy BGA Package .................................................................................. 12 3.0 Pinouts ...
Page 4
SPI Instruction ..................................................................................................43 13.0 Power and Reset Specification .................................................................................56 13.1 Power-Up and Power-Down .................................................................................56 13.2 Reset Specifications ...........................................................................................56 13.3 Power Supply Decoupling....................................................................................57 14.0 Max Ratings and Operating Conditions.....................................................................58 14.1 Absolute Maximum Ratings .................................................................................58 14.2 Operating Conditions..........................................................................................58 14.3 Endurance ........................................................................................................59 ...
Page 5
Numonyx® Omneo™ P8P Datasheet Revision History Date Revision Description December 14th, 2006 0 Initial Advance Information Datasheet March, 2007 1 Advance Information Datasheet Fixed the spelling error and deleted a repeated sentence on page 10 Added Section 2.3 “64-Ball EBGA ...
Page 6
Product Description 1.1 Introduction Numonyx® Omneo™ Phase Change Memory for embedded applications offers all of the best attributes from other memory types in a new, highly scalable and flexible technology. Phase Change Memory (PCM new type of ...
Page 7
Numonyx® Omneo™ P8P Datasheet 1.2 Product Overview The Numonyx® Omneo™ P8P PCM provides the convenience and ease of NOR flash emulation while providing a set of Super Set features that exploit the inherent capabilities of the PCM technology. The device ...
Page 8
Bit Alterability or Overwrite: PCM technology supports the ability to change each memory bit independently from without an intervening block erase operation. Bit Alterability enables software to write to the non-volatile memory ...
Page 9
Numonyx® Omneo™ P8P Datasheet 1.3 Memory Map This section covers the memory map for the Top and Bottom boot devices Table 1: Top Parameter Memory Map Programming Region Number August 2010 316144-07 ...
Page 10
Table 2: Bottom Parameter Memory Map Programming Region Number Datasheet 10 Numonyx® Omneo™ P8P Datasheet Size Blk 128-Mbit (KW) 64 130 7F0000-7FFFFF 64 115 700000-70FFFF 64 114 6F0000-6FFFFF 64 99 600000-60FFFF 64 ...
Page 11
Numonyx® Omneo™ P8P Datasheet 2.0 Package Information This section covers the mechanical specifications for the available packages. 2.1 56-Lead TSOP Figure 1: TSOP Mechanical Specifications Z See Notes 1 and 3 Pin 1 See Detail A Detail A Notes: 1. ...
Page 12
Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Lead Thickness c Package Body Length D 1 Package Body Width E Lead Pitch e Terminal Dimension D Lead Tip Length L Lead Count N Lead Tip Angle ...
Page 13
Numonyx® Omneo™ P8P Datasheet Table 4: Easy BGA Package Dimensions Product Information Package Height (128-Mbit) Ball Height Package Body Thickness (128-Mbit) Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball ...
Page 14
Pinouts and Ballouts Figure 3: 56-Lead TSOP Pinout (128-Mbit) 1 A16 2 A15 3 A14 4 A13 5 A12 6 A11 7 A10 A23 10 A22 11 A21 12 VSS 13 VCC 14 WE# 15 WP# ...
Page 15
Numonyx® Omneo™ P8P Datasheet Figure 4: 64-Ball Easy BGA Ballout (128-Mbit Vpp A13 B A2 Vss A9 CE#/S# A14 A10 A12 A15 A11 RST# Vccq ...
Page 16
Signals Table 5: Ball/Pin Descriptions Symbol Type ADDRESS INPUTS: Device address inputs. 128-Mbit: A[23:1] Note: The address bus for TSOP and Easy BGA starts at A1. Numonyx® Omneo™ P8P PCM uses x16 A[MAX:1] Input addressing. The Numonyx® Omneo™ P8P ...
Page 17
Numonyx® Omneo™ P8P Datasheet 5.0 Bus Operations CE and RST assumed to be valid. OE#-low activates the outputs and gates selected data onto the I/ O bus. WE#-low enables device write operations. When the VPP ...
Page 18
When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 5.5 Reset As with any automated device important to ...
Page 19
Numonyx® Omneo™ P8P Datasheet 6.0 Command Set 6.1 Device Command Codes The system CPU provides control of all in-system read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all block-erase ...
Page 20
Table 7: Command Codes and Descriptions Code Device Mode Prepares the CUI for lock configuration. If the next command is not Block-Lock, Unlock, or Lock- 60h Lock Set-Up Down the CUI sets SR.4 and SR.5 to indicate command sequence error. ...
Page 21
Numonyx® Omneo™ P8P Datasheet Table 8: Command Sequences in x16 Bus Mode Mode Command Lock Block Block Unlock Block Lock Lock-down Block Protection Program Protection Lock Protection Program Notes: 1. First command cycle address should be the same as the ...
Page 22
Read Operation Numonyx® Omneo™ P8P PCM has several read modes: • Read array mode: read returns PCM array data from the addressed locations. • Read identifier mode: reads returns manufacturer device identifier data, block lock status, and protection register ...
Page 23
Numonyx® Omneo™ P8P Datasheet Table 10: Device ID Table Device 128 Mb 128 Mb 7.3 Read Query Command The Query space comes to the foreground and occupies the device address range supplied by the Read Query command address. The mode ...
Page 24
Program Operations There are five kinds of write operations available in Numonyx® Omneo™ P8P PCM. • Word Program (40h, or 10h) • Bit Alterable Word Write (42h) • Buffered Program (E8h) • Bit Alterable Buffered Write (EAh) • Buffered ...
Page 25
Numonyx® Omneo™ P8P Datasheet 8.2 Bit Alterable Word Write Command The Bit Alterable Word Write Command executes just like Word Program Command (40h/10h), using a two-write command sequence. The Bit Alterable Write Setup command (42h) is written to the CUI ...
Page 26
Bit Alterable Buffer Write The Bit Alterable Buffer Write command sequence is the same as for Buffer Program. For command sequence see The primary difference between the two Buffer commands is when the Write State Machine starts executing, the ...
Page 27
Numonyx® Omneo™ P8P Datasheet 8.6 Program Suspend Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from the device other than the one being programmed. The Program Suspend command can be issued ...
Page 28
Erase Unlike floating gate flash, PCM does not require a high voltage block erase operation to change all the bits in a block to “1.” bit alterable technology, each bit is capable of independently being changed from ...
Page 29
Numonyx® Omneo™ P8P Datasheet During a suspend, CE current. V must remain at its program level and WP# must remain unchanged while PP in suspend mode. The Resume (D0h) command instructs the WSM to continue writing/erasing and automatically ...
Page 30
Security Mode The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 10.1 Block Locking There are two types of block locking on Numonyx® ...
Page 31
Numonyx® Omneo™ P8P Datasheet Table 13: Block Locking Truth Table V WP# RST# PP ≤ PPLK IH > PPLK IL > PPLK IH 10.1.3 Unlock Block The Unlock Block command unlocks locked blocks (if ...
Page 32
Locking Operations During Erase Suspend Block lock configurations can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. This is useful when another block needs to be updated ...
Page 33
Numonyx® Omneo™ P8P Datasheet Figure 6: Block Locking State Diagram Power-Up/Reset Notes : 1. [a,b,c] represents [WP#, DQ1, DQ0 Don’t Care 2. DQ1 indicates Block Lock -Down status . DQ1 = ‘0’, Lock-Down has not bee issued to ...
Page 34
Note: The Selectable Block Locking will not be indicated in the Zero Latency Block Lock Status. See Section 10.1.6, “Block Lock Status” on page 31 PR-LOCK0 register to determine Block Lock Status for these blocks. Table 15: Selectable OTP Block ...
Page 35
Numonyx® Omneo™ P8P Datasheet 10.2.1 WP# Lock-Down Control for Selectable OTP Lock Blocks Once the block has been permanently locked with OTP bit, WP# at VIH does not override the lock down of the blocks those bits control. 10.2.2 Selectable ...
Page 36
Registers 11.1 Read Status Register The device’s Status Register displays program and erase operation status. A device’s status can be read after writing the Read Status Register command. The Status Register can also be read following a Program, Erase, ...
Page 37
Numonyx® Omneo™ P8P Datasheet 11.1.1 Clear Status Register Command The Clear Status Register command clears the Status Register. The command functions independently of the applied V SR[7:0] and clear (0) bits 2, 6, and 7. Because bits ...
Page 38
For the 2K OTP space, there exists an additional 16-bit lock register called PR_LOCK1. Each bit in the PR_LOCK1 register locks a 128-bit segment of the 2K-OTP space. Therefore, the 16 128-bit segments of the 2K OTP space can be ...
Page 39
Numonyx® Omneo™ P8P Datasheet 11.2.3.1 OTP Protection Register Addressing details Table 18: Protection Register Addressing Word Use ID Offset LOCK Both DBA + 000080h 0 Numonyx DBA + 000081h 1 Numonyx DBA + 000082h 2 Numonyx DBA + 000083h 3 ...
Page 40
Serial Peripheral Interface (SPI) 12.1 SPI Overview A Serial Peripheral Interface has been added as a secondary interface on Numonyx® Omneo™ P8P PCM to enable low cost, low pin count on-board programming. This interface gives access to the P8P ...
Page 41
Numonyx® Omneo™ P8P Datasheet 12.3 SPI Memory Organization The memory is organized as: • 16,772,216 bytes (8 bits each) • 128 sectors (128 Kbytes each) • 131,072 pages (64 bytes each) Each page can be individually programmed (bits are programmed ...
Page 42
Table 6. Memory organization (Continued) Sector 101 CA0000 100 C80000 99 C60000 98 C40000 97 C20000 96 C00000 95 BE0000 94 BC0000 93 BA0000 92 B80000 91 B60000 90 B40000 89 B20000 88 B00000 87 AE0000 86 AC0000 85 AA0000 ...
Page 43
Numonyx® Omneo™ P8P Datasheet Table 6. Memory organization (Continued) Sector 68 880000 67 860000 66 840000 65 820000 64 800000 12.4 SPI Instruction Serial data input D is sampled on the first rising edge of Serial Clock (C) after Chip ...
Page 44
Table 20: Instruction set Instruction Description WREN Write enable WRDI Write disable RDID Read identification RDSR Read status register WRSR Write status register READ Read data bytes FAST_READ Read data bytes at higher speed Page program (Legacy Program) PP Page ...
Page 45
Numonyx® Omneo™ P8P Datasheet 12.4.2 Write disable (WRDI) The write disable (WRDI) instruction resets the write enable latch (WEL) bit. The write disable (WRDI) instruction is entered by driving Chip Select (S#) Low, sending the instruction code, and then driving ...
Page 46
Read identification (RDID) The read identification (RDID) instruction allows to read the device identification data: • Manufacturer identification (1 byte) • Device identification (2 bytes) The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. ...
Page 47
Numonyx® Omneo™ P8P Datasheet 12.4.4 Read status register (RDSR) The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase, write status register is ...
Page 48
Table 7. Protected area sizes Status register contents bit bit 3 bit 2 bit 1 bit ...
Page 49
Numonyx® Omneo™ P8P Datasheet Figure 12: Read status register (RDSR) instruction sequence and data-out sequence Instruction DQ0 High Impedance DQ1 August 2010 316144- ...
Page 50
Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable ...
Page 51
Numonyx® Omneo™ P8P Datasheet 12.4.6 Read data bytes (READ) The device is first selected by driving Chip Select (S#) Low. The instruction code for the read data bytes (READ) instruction is followed by a 3-byte address A[23:0], each bit being ...
Page 52
Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S#) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address A[23:0] and ...
Page 53
Numonyx® Omneo™ P8P Datasheet 12.4.8 Page program (PP) Note: This definition applies to all flavors of Page Program: Legacy Program, Bit-alterable. The page program (PP) instruction allows bytes to be programmed/written in the memory. Before it can be accepted, a ...
Page 54
Figure 16: Page program (PP) instruction sequence Instruction DQ0 Data byte ...
Page 55
Numonyx® Omneo™ P8P Datasheet 12.4.9 Sector erase (SE) The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the ...
Page 56
Power and Reset Specification 13.1 Power-Up and Power-Down Upon power-up the flash memory interface is defined by the SERIAL pin being at Vss (parallel) or Vcc (serial). • During power-up if the SERIAL pin is at Vss the flash ...
Page 57
Numonyx® Omneo™ P8P Datasheet Figure 18: Reset Operation Waveforms (A) Reset during read mode (B) Reset during program or block erase P1 ≤ P2 (C) Reset during program or block erase P1 ≥ P2 (D) VCC Power-up to RST# high ...
Page 58
Max Ratings and Operating Conditions 14.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Table 23: Absolute Maximum Ratings Voltage on any signal (except V , ...
Page 59
Numonyx® Omneo™ P8P Datasheet 14.3 Endurance Numonyx® Omneo™ P8P PCM endurance is different than traditional non-volatile memory. For PCM a “write cycle” is defined as any time a bit changes within a 32-byte page. Table 25: Endurance Parameter Write Cycle ...
Page 60
Electrical Specifications 15.1 DC Current Characteristics Table 26: DC Current Characteristics (1) Sym Parameter I Input Load LI Output 15-0 Leakage V CC Standby, I CCS Power Down 128-Mbit I CCD Asynchronous single word Average f ...
Page 61
Numonyx® Omneo™ P8P Datasheet 15.2 DC Voltage Characteristics Table 27: DC Voltage Characteristics Sym Parameter Notes V Input Low Input High Output Low OL V Output High Lock-Out 1 PPLK PP ...
Page 62
AC Characteristics 16.1 AC Test Conditions Figure 19: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at V timing begins/ends at V case speed occurs at V Figure 20: Transient ...
Page 63
Numonyx® Omneo™ P8P Datasheet 16.3 AC Read Specifications Table 30: AC Read Specifications Num Sym Asynchronous Specifications R1 t Read cycle time AVAV t R2 Address to output valid AVQV R3 t CE# low to output valid ELQV R4 t ...
Page 64
Figure 22: Asynchronous Page Mode Read Timing R2 A[Max:4] [A] A[3:1] CE# [E] OE# [G] R6 DATA [D/Q] Datasheet R10 R10 R3 R4 R108 Q1 Q2 Numonyx® Omneo™ P8P Datasheet R10 R10 R8 R9 R108 R108 Q3 ...
Page 65
Numonyx® Omneo™ P8P Datasheet 16.4 AC Write Specifications Table 31: AC Write Characteristics Num Sym W1 t RST# high recovery to WE# low PHWL W2 t CE# setup to WE# low ELWL W3 t WE# write pulse width low WLWH ...
Page 66
Figure 23: Single-Word Write Timing Address [A] W2 CE# [E} WE# [W] OE# [G] Data [D/Q] W1 RST# [P] WP# Figure 24: Asynchronous Read-to-Write Timing Address [A] CE# [E} OE# [G] WE# [W] Data [D/Q] RST# [P] Note: See sections ...
Page 67
Numonyx® Omneo™ P8P Datasheet Figure 25: Write-to-Asynchronous Read Timing Address [A] W2 CE# [E} WE# [W] OE# [G] Data [D/Q] W1 RST # [P] See sections 7.6 (AC Read Characteristics) and 7.7 (AC Write Characteristics) for the values of Rs ...
Page 68
SPI AC Specifications Sym F Clock Frequency for all instructions except READ ( Clock Frequency for all instructions except READ (- Clock Frequency for READ R T Clock High ...
Page 69
Numonyx® Omneo™ P8P Datasheet Figure 26: Serial Input Timing tCHSL tSLCH C S# tDVCH tCHDX D MSB Q Figure 27: Write Protect Setup and Hold Timing during WRSR when SRWD=1 W/V PP tWHSL S C DQ0 High Impedance DQ1 Figure ...
Page 70
Figure 29: Output Timing - Al13729 S C tCLQV tCLQX tCLQX DQ1 ADDR. DQ0 LSB IN Datasheet 70 tCH tCLQV tCL tQLQH tQHQL Numonyx® Omneo™ P8P Datasheet tSHQZ LSB OUT AI13729 August 2010 316144-07 ...
Page 71
Numonyx® Omneo™ P8P Datasheet 17.0 Program and Erase Characteristics Table 32: Program and Erase Specification (1) Operation Symbol Erasing and Suspending 3 Erase to Suspend W602 W500 Erase Time W501 W600 Suspend Latency W601 Conventional Word Programming (6) Program Time ...
Page 72
... Ordering Information This section defines all active line items that can be ordered. Table 33: Active Line Item Ordering Table (0 to +70 Part Number NP8P128A13BSM60E NP8P128A13TSM60E NP8P128A13B1760E NP8P128A13T1760E Table 34: Active Line Item Ordering Table (-30 to +85 Part Number NP8P128AE3BSM60E NP8P128AE3TSM60E NP8P128AE3B1760E NP8P128AE3T1760E Datasheet 72 Numonyx® Omneo™ P8P Datasheet ...
Page 73
Numonyx® Omneo™ P8P Datasheet Appendix A Supplemental Reference Information A.1 Flow Charts Figure 30: Word Programming or Bit Alterable Write Flowchart WORD PROGRAM or BIT ALTERABLE WORD WRITE PROCEDURE Start Program Setup Write 40h or 42h Word Address Confirm Data ...
Page 74
Figure 31: Write Suspend/Resume Flowchart Start Read Status Write 70h Program Suspend Write B0h Any Address Read Status Register 0 SR SR.2 = Completed 1 Read Array Write FFh Read Array Data Done No Reading Yes Write ...
Page 75
Numonyx® Omneo™ P8P Datasheet Figure 32: Buffer Program or Bit Alterable Buffer Write Flowchart BUFFER PROGRAM or BIT ALTERABLE BUFFER WRITE PROCEDURE Start Device Supports Buffer Use Single Word Writes No Writes? Yes Set Timeout or Loop Counter Get Next ...
Page 76
Figure 33: Block Erase Flowchart Start Block Erase Write 20h Block Address Erase Confirm Write D0h and Block Address Read Status Register Suspend 0 SR.7 = Erase 1 Full Erase Status Check (if desired) Block Erase Complete Read Status Register ...
Page 77
Numonyx® Omneo™ P8P Datasheet Figure 34: Erase Suspend/Resume Flowchart Start Read Status Write 70h Any Address Erase Suspend Write B0h Any Address Read Status Register Read Read or Program Program? Read Array ...
Page 78
Figure 35: Locking Operations Flowchart Start Lock Setup Write 60h Block Address Lock Confirm Write 01,D0,2Fh Block Address Read ID Plane Write 90h Read Block Lock Status Locking No Change? Yes Read Array Write FFh Any Address Lock Change Complete ...
Page 79
Numonyx® Omneo™ P8P Datasheet Figure 36: Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Start Write 0xC0, (Program Setup) PR Address Write PR (Confirm Data) Address & Data Read Status Register 0 SR[ Full Status Check (if desired) ...
Page 80
A.2 Write State Machine Figure 37, “Write State Machine — Next State Table (sheet 1)” on page 80 “Write State Machine — Output Next State Table (Sheet 4)” on page 83 command state transitions based on incoming commands. Figure 37: ...
Page 81
Numonyx® Omneo™ P8P Datasheet Figure 38: Write State Machine — Next State Table (Sheet 2) Command Input to Chip and resulting Chip Next State OTP Setup (4) Confirm (7) (C0H) OTP Setup Ready (Lock Ready Error [Botch]) (Lock Block) BP ...
Page 82
Figure 39: Write State Machine — Output Next State Table (Sheet 3) Word Read Program Array (2) Current chip state Setup (3,4) (FFH) (10H/40H) Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, SM Entry ...
Page 83
Numonyx® Omneo™ P8P Datasheet Figure 40: Write State Machine — Output Next State Table (Sheet 4) Current chip state Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, SM Entry Setup, SM Exit Setup Lock/CR ...
Page 84
A.3 Common Flash Interface The Numonyx® Omneo™ P8P PCM device borrows from the existing standards established for flash memory, and supports the use of the Common Flash Interface (CFI). This appendix defines the data structure or “database” returned by the ...
Page 85
Numonyx® Omneo™ P8P Datasheet Table 36: Example of Query Structure Output of x16- Devices Word Addressing: Offset Hex Code A – 00010h 0051 00011h 0052 00012h 0059 P_ID 00013h LO P_ID 00014h HI P 00015h LO P ...
Page 86
Table 37: Block Status Register Offset Length (1) (BA+2)h 1 Block Lock Status Register BSR.0 Block lock status BSR.1 Block lock-down status BSR.4 EFA Block lock status BSR.5 EFA Block lock-down status BSR 2–3, 6-7: Reserved for future use Table ...
Page 87
Numonyx® Omneo™ P8P Datasheet Table 40: Device Geometry Definition Offset Length “n” such that device size = 2 27h 1 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities ...
Page 88
A.3.4 Numonyx-Specific Extended Query Table Table 41: Primary Vendor-Specific Extended Query (1) Length Offset P = 10Ah (P+0)h 3 Primary extended query table (P+1)h (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII (P+5)h 4 Optional ...
Page 89
Numonyx® Omneo™ P8P Datasheet Table 42: Protection Register Information (1) Length Offset P = 10Ah (P+E)h 1 Number of Protection register fields in JEDEC ID space. “00h,” indicates that 256 protection fields are available (P+F)h 4 Protection Field 1: Protection ...
Page 90
Table 44: Partition and Erase-block Region Information (1) Offset P = 10Ah Bottom Top Number of device hardware-partition regions within the device single hardware partition device (no fields follow). x specifies the number of device partition ...
Page 91
Numonyx® Omneo™ P8P Datasheet Table 45: Partition and Erase-block Region Information Partition Region 1 (Erase Block Type 1) Programming Region Information (P+30)h (P+30)h bits 0– 2^x = Programming Region aligned size (bytes) (P+31)h (P+31)h bits 8–14 = Reserved; ...
Page 92
Table 46: Partition and Erase-block Region Information Datasheet 92 Partition and Erase-block Region Information Address 128 Mbit –B –T 129: --01 --01 12A: --24 --24 12B: --00 --00 12C: --01 --01 12D: --00 --00 12E: --11 --11 12F: --00 --00 ...
Page 93
Numonyx® Omneo™ P8P Datasheet August 2010 316144-07 93 ...
Page 94
Datasheet 94 Numonyx® Omneo™ P8P Datasheet August 2010 316144-07 ...