NP8P128A13BSM60E Micron Technology Inc, NP8P128A13BSM60E Datasheet - Page 36

• Manufacturer Part Number: NP8P128A13BSM60E
• Manufacturer: Micron Technology Inc

Specifications of NP8P128A13BSM60E

• Lead Free Status / Rohs Status: Supplier Unconfirmed

11.0
11.1
Table 17: Status Register Definitions
Datasheet
36
SR.7 = Device Write/Erase Status (DWS)
SR.6 = Erase Suspend Status (ESS)
SR.5 = Erase Status (ES)
SR.4 = Program Status (PS)
SR.3 = V
SR.2 = Program Suspend Status (PSS)
SR.1 = Device Protect Status (DPS)
SR.0 Super Page Write Status (PRW)
0 = Reserved
1 = Reserved
SR.7
DRS
PP
Status (VPPS)
Status Register Bits
0 = Device WSM is Busy
1 = Device WSM is Ready
0 = Erase in progress/
completed
1 = Erase suspended
0 = Successful erase
1 = Erase error
0 = Successful write
1 = Write error
0 = V
1 = V
aborted
0 = Write in progress/
completed
1 = Write suspended
0 = Unlocked
1 = Aborted erase/program
attempt on locked block
Registers
Read Status Register
The device’s Status Register displays program and erase operation status. A device’s
status can be read after writing the Read Status Register command. The Status
Register can also be read following a Program, Erase, or Lock Block command
sequence. Subsequent single reads from the device outputs its status until another
valid command is written.
The last of OE# or CE# falling edge latches and updates the Status Register content.
DQ[7:0] output is the Status Register bits; DQ[15:8] output 00h. See
Register Definitions” on page
Issuing a Read Status, Block Lock, Program, or Erase command to the device places it
in the Read Status mode. Status Register bit SR.7 (DWS — Device Write Status)
provides program/erase status of the device. Status Register bits SR.1-SR.6 present
information about the WSM’s program, erase, suspend, V
mode.
SR.6
ESS
PP
PP
low detect, operation
OK
SR.5
ES
SR.7 indicates erase or program completion in the device. SR.1–6 are invalid
while SR.7 = “0.”
After issuing an Erase Suspend command, the WSM halts and sets (1) SR.7 and
SR.6. SR.6 remains set until the device receives an Erase Resume command.
SR.5 is set (1) if an attempted erase failed.
A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
SR.4 is set (1) if the WSM failed to program.
A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
The WSM indicates the V
provide continuous V
After receiving a Write Suspend command, the WSM halts execution and sets
(1) SR.7 & SR.2, which remains set until a Resume command is received.
If an erase or program operation is attempted to a locked block (if WP# = V
the WSM sets (1) SR.1 and aborts the operation.
Reserved
SR.4
PS
36.
VPPS
SR.3
PP
feedback and isn’t guaranteed when V
PP
level after program or erase starts. SR.3 does not
Notes:
SR.2
PSS
Numonyx® Omneo™ P8P Datasheet
PP
, and block-lock status
SR.1
DPS
Table 17, “Status
PP
< V
PPLK
August 2010
316144-07
PRW
SR.0
IL
),