NP8P128A13BSM60E Micron Technology Inc, NP8P128A13BSM60E Datasheet - Page 28

• Manufacturer Part Number: NP8P128A13BSM60E
• Manufacturer: Micron Technology Inc

Specifications of NP8P128A13BSM60E

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9.0
9.1
9.2
Datasheet
28
Erase
Unlike floating gate flash, PCM does not require a high voltage block erase operation to
change all the bits in a block to “1.” As a bit alterable technology, each bit is capable of
independently being changed from a “0” to a “1” and from a “1” to a “0”. With floating
gate flash, a high voltage potential must be placed in parallel upon a group of bits
called an erase block. Each bit within the block may be changed independently from “1”
to a “0”, but only may be changed from a “1” to a “0” through a grouped erase
operation. To maintain compatibility with legacy flash system software, Numonyx®
Omneo™ P8P PCM mimics or emulates a flash erase by writing each bit within a block
to “1”, thereby emulating flash-style erase.
Block Erase
The system processor writes the Erase Setup command (20h) to the device followed by
a second Confirm (D0h) command write that specifies the address of the block to be
erased. The device during both of the command cycles automatically outputs Status
Register data when the device address is read. See
on page
After writing the command, the device automatically enters read status mode. The
device Status Register bit SR.7 will be set (“1”) when the erase completes. If the erase
fails, Status Register bit SR.5 will be set (“1”). SR.3 = “1” indicates an invalid V
voltage. SR.1 = “1” indicates an erase operation was attempted on a locked block. CE#
or OE# toggle (during polling) updates the Status Register.
If an error bit is set, the Status Register can be cleared by issuing the Clear Status
Register command before attempting the next operation. The device will remain in
Status Register mode until another command is written to the device. Any command
can follow once erase completes. Only one block can be in erase mode at a time.
Erase Suspend Command
The Write/Erase Suspend command halts an in-progress write or erase operation. The
command can be issued at any device address. The Suspend command allows data to
be accessed from memory locations other than the one block being written or the block
being erased.
A Write operation can be suspended to perform reads only at any location except the
address being programmed. An Erase operation can be suspended to perform either a
write or a read operation within any block except the block that is erase suspended. A
Write command nested within a suspended Erase can subsequently be suspended to
read yet another location. Once the write/erase process starts, the Suspend command
requests that the WSM suspend the write/erase sequence at predetermined points in
the algorithm. An operation is suspended when status bits SR.7 and SR.6 and/or SR.2
display “1.” t
To read data from other blocks within the device (other than an erase-suspended
block), a Read Array command can be written. During Erase Suspend, a Write
command can be issued to a block other than the erase-suspended block. Block erase
cannot resume until write operations initiated during erase suspend complete. Read
Array, Read Status Register, Read Identifier (ID), Read Query, and Write Resume are
valid commands during Write or Erase Suspend. Additionally, Clear Status Register,
Program, Write Suspend, Erase Resume, Lock Block, Unlock Block, and Lock-Down
Block are valid commands during Erase Suspend.
76.
SUSP/P
/t
SUSP/E
specifies suspend latency.
Section 33, “Block Erase Flowchart”
Numonyx® Omneo™ P8P Datasheet
August 2010
316144-07
PP