NP8P128A13BSM60E Micron Technology Inc, NP8P128A13BSM60E Datasheet - Page 19

• Manufacturer Part Number: NP8P128A13BSM60E
• Manufacturer: Micron Technology Inc

Specifications of NP8P128A13BSM60E

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Numonyx® Omneo™ P8P Datasheet
6.0
6.1
Table 7:
August 2010
316144-07
Code
EAh
DEh
D0h
D0h
B0h
D0h
FFh
70h
90h
98h
50h
40h
10h
42h
E8h
20h
Command Codes and Descriptions
Read Array
Read Status
Register
Read ID Code
Read Query
Clear Status
Register
Program
Set-Up
Alt Set-up
Bit Alterable
Write
Buffered
Program
Bit Alterable
Buffered Write
Buffered Write
Confirm
Block Erase
Set-Up
Erase Confirm
Write or
Erase Suspend
Suspend
Resume
Buffer Program
Device Mode
Command Set
Device Command Codes
The system CPU provides control of all in-system read, write, and erase operations of
the device via the system bus. The on-chip Write State Machine (WSM) manages all
block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the flash device is controlled.
on all 1s
Places device in read array mode so that data signals output array data on DQ[15:0].
Places the device in Status Register read mode. Status data is output on DQ[7:0]. The device
automatically enters this mode after a program or erase command is issued to it.
Puts the device in read identifier mode. Device reads from the addresses output manufacturer/
device codes, block lock status, or protection register data on DQ[15:0].
Puts the device in read query mode. Device reads from the address given outputting the
Common Flash Interface information on DQ[7:0]
The WSM can set the Status Register’s block lock (SR.1), V
erase (SR.5) status bits to “1” but cannot clear them. Device reset or
the Clear Status Register command at any device address clears those bits to “0.”
This preferred program command’s first cycle prepares the CUI for a program operation. The
second cycle latches address and data and executes the WSM Program algorithm at this
location. Status Register updates occur when CE# or OE# is toggled. A Read Array command is
required to read array data after programming.
Equivalent to a Program Set-Up command (40h).
The command sequence is the same as Word Program (40h). The difference is the state of the
PCM memory cell can change from a 0 to 1 or 1 to 0, unlike a flash memory cell, which can only
change from 1 to 0 during programming.
This command loads a variable number of bytes up to the buffer size 32 words onto the
program buffer.
This command sequence is the similar to Buffered Program, but the buffer write command is bit
alterable or overwrite operation. The command sequence is the same as E8h.
This command is the same as Buffered Program, but user indicates that the pagee is already
set to all 1s. The command sequence is the same as E8h
The confirm command is issued after the data streaming for writing into the buffer is done. This
initiates the WSM to carry out the buffered programing algorithm.
Prepares the CUI for Block Erase. The device emulates erasure of the block addressed by the
Erase Confirm command by writing all ones. If the next command is not Erase Confirm, the CUI
If the first command was Erase Set-Up (20h), the CUI latches address and data then emulates
erasure of the block indicated by the Erase confirm cycle address.
This command issued at any device address initiates suspension of the currently executing
program/erase operation. The Status Register, invoked by a Read Status Register command,
indicates successful suspend operation by setting (1) status bits SR.2 (write suspend) or SR.6
(erase suspend) and SR.7. The WSM remains in the Suspend mode regardless of the control
signal states, except RST# = V
This command issued at any device address resumes suspended program or erase operation.
(a) sets Status Register bits SR.4 and SR.5 to “1,”
(b) places the device in the read Status Register mode, and
(c) waits for another command.
IL
.
Description
PP
(SR.3), program (SR.4), and
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