NP8P128A13BSM60E Micron Technology Inc, NP8P128A13BSM60E Datasheet - Page 56

• Manufacturer Part Number: NP8P128A13BSM60E
• Manufacturer: Micron Technology Inc

Specifications of NP8P128A13BSM60E

• Lead Free Status / Rohs Status: Supplier Unconfirmed

13.0
13.1
13.2
Table 22: Power and Reset
Datasheet
56
Notes:
1.
2.
3.
4.
5.
6.
7.
Num
P1
P2
P3
t
t
t
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
When RST# is tied to the V
When RST# is tied to the V
Reset completes within t
Symbol
PLPH
PLRH
VCCPH
Power and Reset Specification
Power-Up and Power-Down
Upon power-up the flash memory interface is defined by the SERIAL pin being at Vss
(parallel) or Vcc (serial).
After the interface is defined it can not be changed until a full power-down is completed
and a power-up sequence is reinitiated.
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
V
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
CC
• During power-up if the SERIAL pin is at Vss the flash memory will be a x16 parallel
• During power-up if the SERIAL pin is at Vcc the flash memory will be a SPI
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
V
CC
interface.
interface.
and V
Power valid to RST# de-assertion (high)
CCQ
PLPH
PLPH
should attain their minimum operating voltage before applying V
CC
CCQ
if RST# is asserted while no erase or program operation is executing.
is < t
supply, device will not be ready until t
Parameter
supply, device will not be ready until t
PLPH
MIN , but this is not guaranteed.
(1)
VCCPH
VCCPH
Min
100
100
-
-
after V
after V
Numonyx® Omneo™ P8P Datasheet
CC
CC
Max
≥ V
40
40
≥ V
-
-
CCMIN
CCMIN
.
.
Unit
ns
us
August 2010
316144-07
PP
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
Notes
.