NP8P128A13BSM60E Micron Technology Inc, NP8P128A13BSM60E Datasheet - Page 52

• Manufacturer Part Number: NP8P128A13BSM60E
• Manufacturer: Micron Technology Inc

Specifications of NP8P128A13BSM60E

• Lead Free Status / Rohs Status: Supplier Unconfirmed

12.4.7
Figure 15: Read data bytes at higher speed (FAST_READ) instruction sequence
Datasheet
52
DQ0
DQ1
S
C
DQ0
DQ1
S
C
Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S#) Low. The instruction code for the
read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte
address A[23:0] and a dummy byte, each bit being latched-in during the rising edge of
Serial Clock (C). Then the memory contents, at that address, are shifted out on serial
data output (Q) at a maximum frequency f
The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single read data bytes at higher speed
(FAST_READ) instruction. When the highest address is reached, the address counter
rolls over to 000000h, allowing the read sequence to be continued indefinitely.
The read data bytes at higher speed (FAST_READ) instruction is terminated by driving
Chip Select (S#) High. Chip Select (S#) can be driven High at any time during data
output. Any read data bytes at higher speed (FAST_READ) instruction, while an erase,
program, write, or cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
and data-out sequence
0
7
32 33 34
6
1
High Impedance
Dummy byte
5
2
Instruction
3
4
35
3
4
36 37 38 39 40 41 42 43 44 45 46
5
2
1
6
0
7
MSB
23
8
7
22 21
6
9 10
24-bit address
DATA OUT 1
5
4
3
28 29 30 31
3
2
2
(1)
1
1
0
0
47
C
MSB
, during the falling edge of Serial Clock (C).
7
6
DATA OUT 2
5
4
3
Numonyx® Omneo™ P8P Datasheet
2
1
0
MSB
AI13737b
7
August 2010
316144-07