Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 13

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM011001-0601
Process
Read
Write
DMA Write
DMA Read
DMA Write
DMA Read
In the DMA Read with Byte Swap enabled:
Byte Swap Select
2.3 I/O INTERFACE CAPABILITIES
The ISCC offers the choice of Polling, Interrupt (vectored
or non-vectored), and DMA Transfer modes to transfer da-
ta, status, and control information to and from the CPU.
2.3.1 Polling
In this mode all interrupts and the DMA’s are disabled.
Three status registers in the SCC are automatically updat-
ed whenever any function is performed. For example, end-
of-frame in SDLC mode sets a bit in one of these status
registers. With polling, the CPU must periodically read a
status register until the register contents indicate the need
for some CPU action to be taken. Only one register in the
SCC cell needs to be read; depending on the contents of
the register, the CPU either reads data, writes data, or sat-
isfies an error condition. Two bits in the register indicate
the need for data transfer. An alternative is to poll the In-
terrupt Pending register to determine the source of an in-
terrupt. The status for both SCC channels resides in one
register.
2.3.2 Interrupts
When the ISCC responds to an Interrupt Acknowledge sig-
nal (INTACK) from the CPU, an interrupt vector is placed on
the data bus. Both the SCC and the DMA contain vector
registers. Depending on the source of interrupt, one of these
vectors is returned, either unmodified or modified by the in-
terrupt status to indicate the exact cause of the interrupt.
Each of the six sources of interrupt in the SCC (Transmit,
Receive, and External/Status interrupts in both channels)
and each DMA channel has three bits associated with the
Table 2-1. ISCC Bus Access Summary
0
0
1
1
Enable
Byte
X
X
0
0
1
1
Select
Swap
A0
X
X
X
X
X
0
0
1
0
1
Lower
8 Bits
data
data read
data
data read
data
depends
upon A0
(see below)
ISCC Accepts Data
Upper 8 Bits of Bus
Lower 8 Bits of Bus
Lower 8 Bits of Bus
Upper 8 Bits of Bus
Action on
Bus Upper8
Bits
same data
data ignored
same data
data ignored
same data
In this table DMA read refers to a DMA controlled transfer
from memory to the ISCC and DMA write refers to a DMA
controlled transfer from the ISCC to memory. Read refers
to a normal peripheral transaction where the CPU reads
data from the ISCC and Write refers to a normal peripheral
transaction where the CPU writes data to the ISCC.
interrupt source: Interrupt Pending (IP), Interrupt Under
Service (IUS), and Interrupt Enable (IE). If the IE bit is set
for any given source of interrupt, then that source can re-
quest interrupts. The only exception to this rule is when the
associate Master Interrupt Enable (MIE) bit is reset, then
no interrupts are requested. Both the SCC cell and the
DMA have an associated MIE bit. The IE bits in the SCC
cell are write only, but the IE bits in the DMA are read/write.
The ISCC provides for nesting of interrupt sources with an
interrupt daisy chain using the IEI, IEO, and /INTACK pins.
As a microprocessor peripheral, the ISCC may request an
interrupt only when no higher priority device is requesting
one, e.g., when IEI is High. If the device in question re-
quests an interrupt, it enables the /INT signal. The CPU
then responds with /INTACK, and the interrupting cell plac-
es the vector on the data bus.
In the ISCC, the IP bit signals a need for interrupt servic-
ing. When an IP bit is 1 and the IEI input pin is High, the
/INT signal is activated, requesting an interrupt. In the SCC
cell, if the IE bit is not set, then the IP for that source can
never be set. The IP bits in the DMA cell are set indepen-
dent of the IE bit.
The IUS bits signal that an interrupt request is being ser-
viced. If an IUS is set, all interrupt sources of lower pri-
ority in the ISCC and external to the ISCC are prevented
from requesting interrupts. The internal interrupt sourc-
es are inhibited by the state of the internal daisy chain,
while lower priority devices are inhibited by the IEO out-
put of the ISCC being pulled Low and propagated to
Z16C35 ISCC™ User’s Manual
Interfacing the ISCC™
2-3
2