Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 50

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z16C35ISCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
Up to two modem control signals associated with the re-
ceiver are available in synchronous modes: DTR/REQ and
DCD. The /DTR//REQ pin carries the inverted state of the
DTR bit (D7) in WR5 unless this pin has been programmed
to carry a DMA Request signal. The /DCD pin is ordinarily
a simple input to the DCD bit in RR0. However, if the Auto
Enables mode is selected by setting D5 of WR3 to “1”, this
pin becomes an enable for the receiver. Then if Auto En-
ables is ON and the /DCD pin is High the receiver is dis-
abled; while the /DCD pin is Low the receiver is enabled.
The initialization sequence for the receiver in character-
oriented mode is WR4 first, to select the mode, then WR10
to modify it if necessary, WR6 and WR7 to program the
sync characters and then WR3 and WR5 to select the var-
ious options. At this point the other registers should be ini-
tialized as necessary. When all this is completed the re-
ceiver is enabled by setting bit 0 of WR3 to a one. A
summary is shown in Table 4-9.
4.3.3 Transmitter/Receiver Synchronization
The
synchronization function that may be used to guarantee
that the character boundaries for the received and
transmitted data are the same. In this mode the receiver is
in Hunt and the transmitter is idle, sending either all “1s” or
all “0s”. When the receiver recognizes a sync character, it
There are several restrictions on the use of this feature in
the ISCC. First, it will only work with 6-bit, 8-bit or 16-bit
sync characters, and the data character or eight bits with
4-16
ISCC
contains
TxD
RxD
a
Figure 4-10. Transmitter to Receiver Synchronization
transmitter-to-receiver
Sync
Sync
Direction of message flow
Sync
leaves Hunt mode and one character time later the
transmitter
characters. Beyond this point the receiver and transmitter
are again completely independent, except that the
character boundaries are now aligned. This is shown in
Figure 4-10.
an 8-bit or 16-bit sync character. Of course, the receive
and transmit clocks must have the same rate as well as the
proper phase relationship.
Register
WR4
WR10
WR4
WR6
WR7
WR3
WR3
WR4
WR5
WR10
WR0
WR3
WR5
WR3
Receiver Leaves Hunt
Sync
Table 4-9. Initializing the Receiver in
is
Character Oriented Mode
Bit No
4-5
4-5
0-7
0-7
6-7
0-1
7-6
enabled
0
1
4
2
7
0
7
5
Description
Select sync character
Length
Select external sync
Sync character, lower byte
Sync character, upper byte
Sync character inhibit
Enter hunt mode
Number of bits/character
Select parity
Select CRC
CRC generator initial state
Reset CRC generator
CRC enable
DTR/REQ
Auto enableh
and
begins
UM011001-0601
sending
sync