Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 84

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z16C35ISCC™ User’s Manual
Register Descriptions
5.5 READ REGISTERS (Continued)
5.5.4 Read Register 3
RR3 is the interrupt Pending register. The status of each
of the interrupt Pending bits in the SCC cell is reported in
this register. This register exists only in Channel A. If this
register is accessed in Channel B, all “0’s” are returned.
The two unused bits are always returned as “0”. Figure 5-
21 shows the bit positions for RR3.
5.5.5 Read Register 8
RR8 is the Receive Data register.
5.5.6 Read Register 10
RR10 contains some miscellaneous status bits. Unused
bits are always “0”. Bit position for RR10 are shown in Fig-
ure 5-22.
5-24
Read Register 3
D7
Read Register 10
D7
* Always 0 in B Channel
D6
D6
D5 D4 D3 D2 D1 D0
D5 D4 D3 D2 D1 D0
Figure 5-22. Read Register 10
Figure 5-21. Read Register 3
Channel B Ext/Status IP
Channel B Tx IP
Channel B Rx IP
Channel A Ext/Status IP
Channel A Tx IP
Channel A Rx IP
0
0
0
On Loop
0
0
Loop Sending
0
Two Clocks Missing
One Clock Missing
P R E L I M I N A R Y
*
Bit 7 is the One Clock Missing status
While operating in the FM mode, the DPLL sets this bit to
“1” when it does not see a clock edge on the incoming lines
in the window where it expects one. This bit is latched until
reset by a Reset Missing Clock or Enter Search Mode
command in WR14. In the NRZI mode of operation and
while the DPLL is disabled, this bit is always “0”.
Bit 6 is the Two Clocks Missing status
While operating in the FM mode, the DPLL sets this bit to
“1” when it does not see a clock edge in two successive
tries. At the same time the DPLL enters the Search mode.
This bit is latched until reset by a Reset Missing Clock or
Enter Search Mode command in WR14, bit 5-7. In the
NRZI mode of operation and while the DPLL is disabled,
this bit is always “0”.
Bit 4 is the Loop Sending status
This bit is set to “1” in SDLC Loop mode while the transmit-
ter is in control of the Loop, that is, while the ISCC is ac-
tively transmitting on the loop. This bit is reset at all other
times.
This bit can be polled in SDLC mode to determine when
the closing flag has been sent.
Bit 1 is the On Loop status
This bit is set to “1” while the ISCC is actually on loop in
SDLC Loop mode. This bit is set to “1” in the X21 mode
(Loop mode selected while in monosync) when the trans-
mitter goes active. This bit is “0” at all other times. This bit
can also be polled in SDLC mode to determine when the
closing flag has been sent.
5.5.7 Read Register 12
RR12 returns the value stored in WR12, the lower byte of
the time constant for the baud rate generator. Figure 5-23
shows the bit positions for RR12.
Read Register 12
D7
D6
D5 D4 D3 D2 D1 D0
Figure 5-23. Read Register 12
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
UM011001-0601
Lower
Byte of
Time
Constant