Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 39

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM011001-0601
2. Data field - typically 5-8 bits wide.
3. Parity bit - optional, provides mechanism for checking
4. Data + Parity bit contains odd number of 1s (odd
Stop bit(s) - provides a minimum interval between the end
of one character and the beginning of the next.
The ISCC™ supports Asynchronous mode with a number
of programmable options including the number of bits per
character, the number of stop bits, the clock factor, modem
interface signals and break detect and generation.
Asynchronous mode is selected by programming the de-
sired number of stop bits in D3 and D2 or WR4. Program-
ming these two bits with other than “00” places both the re-
ceiver and transmitter in Asynchronous mode. In this
mode, the ISCC ignores the state of bits D4, D3, and D2 of
WR3, bits D5 and D4 of WR4, bits D2 and D0 of WR5, all
of WR6 and WR7 and all of WR10 except D6 and D5. Bits
that are ignored may be programmed with “1” or “0” or not
at all. See Table 4-1 below.
4.2.1 Asynchronous Transmit
Characters are loaded from the transmit buffer to the shift
register where they are given a start bit and a parity bit (if
programmed), and are shifted out to the TxD pin. Each
time the transmit buffer becomes empty the Tx Empty bit
in RR0 is set to 1 and, optionally, an interrupt or DMA re-
quest can be generated.
The number of bits transmitted per character is controlled
both by Bits D6 and D5 in WR5, and the way the data is
formatted within the transmit buffer. The bits in WR5 allow
the option of five, six, seven, or eight bits per character.
When five bits per character is selected the data may be
formatted before being written to the transmit buffer to al-
low transmission of from one to five bits per character.
Register
WR3
WR4
WR5
WR6
WR7
WR10
character validity, transmitter and receiver agree that:
parity) or Data + Parity bit contains even number of 1s
(even parity).
Table 4-1. Write Register Bits Ignored
D7
x
x
x
in Asynchronous Mode
D6
x
x
D5
x
x
x
D4
x
x
x
x
x
D3
x
x
x
x
D2
x
x
x
x
x
D1
x
x
x
D0
x
x
x
x
This formatting is shown in Table 4-2.
For five or less bits per character selection in WR5, the fol-
lowing encoding is used in the data sent to the transmitter.
D is the data bit(s) to be sent.
In all cases the data must be right-justified, with the un-
used bits being ignored except in the case of five bits or
less per character.
An additional bit, carrying parity information, may be auto-
matically appended to every transmitted character by set-
ting bit D0 of WR4 to “1”. This bit is sent in addition to the
number of bits specified in WR4 or by the data format. The
parity sense is selected by bit D1 of WR4. If this bit is set
to “1”, the transmitter sends even parity, if set to “0”, the
parity is odd.
The ISCC may be programmed to accept a transmit clock
that is one, sixteen, thirty-two, or sixty-four times the data
rate. This is selected by bits D7 and D6 of WR4, in com-
mon with the clock factor for the receiver. Note that the
chosen clock factor may restrict the number of stop bits
that may be transmitted. In particular, when the clock rate
and data rate are identical, one-and-a-half stop bits are not
allowed. If any length other than one stop bit is desired in
the times one mode, only two stop bits may be used.
There are two modem control signals associated with the
transmitter provided by the ISCC, namely /RTS and /CTS.
The /RTS pin is a simple output that carries the inverted
state of the RTS bit (D1) in WR5, unless the Auto Enables
bit (D5) is set in WR3. When Auto Enables is set, the /RTS
pin will immediately go Low when the RTS bit is set. How-
ever, when the RTS bit is reset, the /RTS pin remains Low
until the transmitter is completely empty and the last stop
bit has left the TxD pin. Thus the /RTS pin may be used to
disable external drivers for the transmit data.
D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
1
0
Bit 7
1
1
1
0
0
0
0
1
1
Table 4-2. Transmit Bits per Character
1
1
0
0
0
D
1
0
0
0
D
D
0
0
0
Bit 6
0
1
0
1
D
D
D
0
0
Z16C35ISCC™ User’s Manual
Data Communication Modes
D
D
D
D
0
5 or less bits/character
7 bits/character
6 bits/character
8 bits/character
D
D
D
D
D
Sends one data bit
Sends two data bits
Sends three data bits
Sends four data bits
Sends five data bits
4-5
4