Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 74

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z16C35ISCC™ User’s Manual
Register Descriptions
5.4 WRITE REGISTERS (Continued)
Bit 4 is the Status High//Status Low control bit
This bit controls which vector bits the SCC cell will modify
to indicate status. When set to “1,” the SCC cell modifies
bits V6, V5, and V4 according to Table 5-7. When set to
“0,” the SCC cell modifies bits V1, V2, and V3 according to
Table 5-5. This bit controls status in both the vector re-
turned during an interrupt acknowledge cycle and the sta-
tus in RR2B. This bit is reset by a hardware reset.
Bit 3 is the Master Interrupt Enable
This bit is set to 1 to globally enable interrupts, and cleared
to zero to disable interrupts. Clearing this bit to zero forces
the IEO pin to follow the state of the IEI pin unless there is
an IUS bit set in the SCC cell. No IUS bit can be set after
the MIE bit is cleared to zero. This bit is reset by a hard-
ware reset.
Bit 2 is the Disable Lower Chain control bit
The Disable Lower Chain bit can be used by the CPU to
control the interrupt daisy-chain. Setting this bit to “1” forc-
es the IEO pin Low, preventing lower priority devices on
the daisy-chain from requesting interrupts. This bit is reset
by a hardware reset. (Note that in the ISCC this will also
prevent the DMA cell from requesting interrupts.)
Bit 1 is the No Vector select bit
The No Vector bit controls whether or not the ISCC will re-
spond to an interrupt acknowledge cycle by placing a vec-
tor on the data bus if the ISCC is the highest priority device
requesting an interrupt. If this bit is set, no vector is re-
turned; i.e., AD7-AD0 remain three-stated during an inter-
rupt acknowledge cycle, even if the ISCC is the highest pri-
ority device requesting an interrupt.
Bit 0 is the Vector Includes Status control bit
The Vector Includes Status Bit controls whether or not the
SCC cell will include status information in the vector it plac-
es on the bus in response to an interrupt acknowledge cy-
cle. If this bit is set, the vector returned is variable, with the
5-14
V3
V4
0
0
0
0
1
1
1
1
Table 5-7. Interrupt Vector Modification
V2
V5
0
0
1
1
0
0
1
1
V1
V6
0
1
0
1
0
1
0
1
Status High/Status Low =0
Status High/Status Low =1
Ch B Transmit Buffer Empty
Ch B External/Status Change
Ch B Receive Char. Available
Ch B Special Receive Condition
Ch A Transmit Buffer Empty
Ch A External/Status Change
Ch A Receive Char. Available
Ch A Special Receive Condition
P R E L I M I N A R Y
variable field depending on the highest priority IP that is
set. Table 5-5 shows the encoding of the status informa-
tion. This bit is ignored if the No Vector (NV) bit is set.
5.4.11 Write Register 10 (Miscellaneous
Transmitter/Receiver Control Bits)
WR10 contains miscellaneous control bits for both the re-
ceiver and the transmitter. Bit positions for WR10 are
shown in Figure 5-11.
Bit 7 is the CRC Presets 1//0 select bit
This bit specifies the initialized condition of the receive
CRC checker and the transmit CRC generator. If this bit is
set to “1,” the CRC generator and checker are preset to
“1.” If this bit is set to “0,” the CRC generator and checker
are preset to “0.” Either option can be selected with either
CRC polynomial. In SDLC mode, the transmitted CRC is
inverted before transmission and the received CRC is
checked against the bit pattern “0001110100001111.” This
bit is reset by a channel or hardware reset. This bit is ig-
nored in Asynchronous mode.
Bits 6 and 5 are the Data Encoding select bits
These bits control the coding method used for both the
transmitter and the receiver, as illustrated in Table 5-8. All of
the clocking options are available for all coding methods.
The DPLL in the ISCC is useful for recovering clocking infor-
mation in NRZI and FM modes. Any coding method can be
used in X1 clock mode. A hardware reset forces NRZ mode.
Timing for the various modes is shown in Figure 5-12.
Write Register 10
D7
D6
0
0
1
1
D5 D4 D3 D2 D1 D0
0
1
0
1
Figure 5-11. Write Register 10
NRZ
NRZI
FM1 (Transition = 1)
FM0 (Transition = 0)
6 Bit/8 Bit Sync
Loop Mode
Abort/Flag On Underrun
Mark/Flag Idle
Go Active On Poll
CRC Preset I/O
UM011001-0601