Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 137

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM011001-0601
Note: Parameter numbers in this table are the numbers in the Z180 technical manual.
During an Interrupt Acknowledge cycle, the SCC requires
both /INTACK and /RD to be active at certain times. Since
the Z180 does not issue either /INTACK or /RD, external
logic generates these signals.
The Z180 is in a Wait condition until the vector is valid. If
there are other peripherals added to the interrupt priority
daisy chain, more Wait states may be necessary to give it
time to settle. Allow enough time between /INTACK active
and /RD active for the entire daisy chain to settle.
No
13
14
15
38
39
40
41
42
43
No
10
14
15
16
28
29
30
Symbol
TsIAi(RD)
ThIA(RD)
ThIA(PC)
TwRDA
TwRDA
TdRDA(DR)
TsIEI(RDA)
ThIEI(RDA)
TdIEI(IEO)
Symbol
tM1D1
tM1D2
tDRS
tDRH
tIOD1
tIOD2
tIOD3
Table 11. Z180 Timing Parameters Interrupt Acknowledge Cycles (Worst Case Z180)
Table 10. 10 MHz SCC Timing Parameters for Interrupt Acknowledge Cycle
Parameter
/INTACK Low to /RD Low Setup
/INTACK High to /RD High Hold
/INTACK to PCLK High Hold
/INTACK Low to /RD Low Delay
(Acknowledge)
/RD (Acknowledge) Width
/RD Low (Acknowledge) to
Read Data Valid Delay
IEI to /RD Low (Acknowledge)
Setup Time
IEI to /RD High (Acknowledge)
Hold Time
IEI to IEO Delay
Parameter
Clock High to /M1 Low
Clock High to /M1 High
Data to Clock Setup
Data Read Hold Time
Clock LOW to /IORQ Low
Clock LOW to /IORQ High
/M1 Low to /IORQ Low Delay
There is no need of decoding the RETI instruction used by
the Z80 peripherals since the SCC daisy chain does not
use IP, except during Interrupt Acknowledge. The SCC
and other Z8500 peripherals have commands that reset
the individual IUS flag.
External Interface for Interrupt Acknowledge Cycle: The
bottom half of Figure 14 is the interface logic for the
Interrupt Acknowledge cycle.
The Z180™ Interfaced with the SCC at MHZ
Min
130
125
125
Min
200
30
95
25
0
0
0
Max
Max
120
175
60
60
50
50
Application Note
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7-17
7