Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 88

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z16C35ISCC™ User’s Manual
Register Descriptions
5.6 DMA CELL REGISTER DESCRIPTIONS (Continued)
Bit combination 001 resets the Interrupt Pending (IP) bit in
the selected DMA channel(s).
Bit combination 010 resets the Interrupt Under Service
(IUS) bit in the selected DMA channel(s).
Bit combination 011 resets both the Interrupt Pending (IP)
bit and the Interrupt Under Service (IUS) bit in the selected
DMA channel(s).
Bit combination 100 is Reserved.
Bit combination 101 sets the Interrupt Pending (IP) bit in
the selected DMA channel(s).
Bit combination 110 sets the Interrupt Under Service (IUS)
bit in the selected DMA channel(s).
Bit combination 111 sets both the Interrupt Pending (IP) bit
and the Interrupt Under Service (IUS) bit in the selected
DMA channel(s).
Bit 4 is Reserved. (This bit should be programmed as a
zero to avoid conflicts with future versions of this device.)
Bits 3 through 0 select the channel to which the command
is to apply. More than one of these bits may be set for the
command; the command is applied to all of the DMA chan-
nels whose bits are set in this field: (These bits are not
stored and must be written with each command.)
Bit 3, when set, applies the command to the Receive A
DMA.
Bit 2, when set, applies the command to the Transmit A
DMA.
Bit 1, when set, applies the command to the Receive B
DMA.
Bit 0, when set, applies the command to the Transmit B
DMA.
5.6.6 Interrupt Status Register
This is a read only register which shares its address with
the Interrupt Command Register. The bits in this register
reflect the status of the Interrupt Pending (IP) and Interrupt
Under Service (IUS) bits in the DMA channels. The bit po-
sitions for this register are shown in Figure 5-31.
Bit 7 reflects the Receive A DMA Interrupt Under Service
status. This bit can be set or cleared through a command
(see Interrupt Command Register). This bit is set to 1 au-
tomatically during an interrupt acknowledge if this is the
5-28
P R E L I M I N A R Y
highest priority interrupt pending. This is the highest prior-
ity pending interrupt if the corresponding Interrupt Pending
bit is set to 1, if the Interrupt Enable bit for this interrupt is
set to 1, if the IEI input to the ISCC is 1, if the DMA cell
Master Interrupt Enable bit is set to 1, if there are no SCC
cell interrupts pending, and if there is no other DMA chan-
nel with an interrupt pending that is at a higher priority level
(see DMA Control Register for priority programming).
Bit 6 reflects the Transmit A DMA Interrupt Under Service
status. The function of this bit is identical to that for bit 7.
Bit 5 reflects the Receive B DMA Interrupt Under Service
status. The function of this bit is identical to that for bit 7.
Bit 4 reflects the Transmit B DMA Interrupt Under Service
status. The function of this bit is identical to that for bit 7.
Bit 3 reflects the Receive A DMA Interrupt Pending (IP)
status. This bit can be set or cleared through a command
(see Interrupt Command Register). This bit will be set to 1
automatically when a Receive A DMA interrupt condition
occurs. An interrupt will be requested if the corresponding
Interrupt Enable bit is set to 1, if the DMA Master Interrupt
Enable bit is set to 1, and if the ISCC IEI input is 1, and if
the corresponding IUS bit is 0.
Bit 2 reflects the Transmit A DMA Interrupt Pending status.
The function of this bit is identical to that for bit 3.
Bit 1 reflects the Receive B DMA Interrupt Pending status.
The function of this bit is identical to that for bit 3.
Bit 0 reflects the Transmit B DMA Interrupt Pending status.
The function of this bit is identical to that for bit 3.
Address: 00011 (Read)
D7
Figure 5-31. Interrupt Status Register
D6
D5 D4 D3 D2 D1 D0
Tx A DMA IP
Tx B DMA IP
Rx B DMA IP
Rx A DMA IP
Tx B DMA IUS
Rx B DMA IUS
Tx A DMA IUS
Rx A DMA IUS
UM011001-0601