Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 55

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM011001-0601
Most bit-oriented protocols allow an arbitrary number of
bits between opening and closing flags. The ISCC allows
for this by providing three bits of Residue Code in RR1 that
indicates which bits in the last three bytes transferred from
the receive data FIFO by the processor are actually valid
data bits (and not part of the frame check sequence or
CRC). Table 4-12 gives the meanings of the different
As indicated in the table, these bits allow the processor to
determine those bits in the information (and not CRC) field.
This allows transparent retransmission of the received
frame. The Residue Code bits do not go through a FIFO so
they change in RR1 when the last character of the frame
Residue Code
2 1 0
100
010
110
001
101
011
111
000
8B/C 7B/C
Change from Five to Eight
0
0
0
0
0
0
1
2
Change from Eight to Five
Bits in Previous Byte
0
0
0
0
0
0
0
6B/C
0
0
0
0
0
0
Figure 4-13. Changing Character Length
Time
5B/C
Table 4-12. Residue Codes
0
0
0
0
0
Bits in Second Previous Byte
8B/C 7B/C
3
4
5
6
7
8
8
8
13
21
29
34
39
8
codes for the four different character length options. The
valid data bits are right-justified, that is to say if the number
of valid bits given by the table is less than the character
length, then the bits that are valid are the right-most or
least significant bits. It should also be noted that the Resi-
due Code is only valid at the time when the End of Frame
bit in RR1 is set to 1.
is loaded into the receive data FIFO. If there are any char-
acters already in the receive data FIFO the Residue Code
will be updated before they are read by the processor.
12
20
28
33
38
1
2
3
4
5
6
7
7
Receive Data Buffer
11 10 9
19 18 17 16 15 14
27 26 25 24 23 22
32 31 30 29 28 27
37 36 35 34 33 32
6
6B/C
0
0
1
2
3
4
5
4
5B/C
3
8
0
0
0
0
1
2
7
Bits in Third Previous Byte
8B/C 7B/C
1
6
Z16C35ISCC™ User’s Manual
Data Communication Modes
8
8
8
8
8
8
8
8
5 Bits
8 Bits
8 Bits
5 Bits
5 Bits
7
7
7
7
7
7
7
6B/C
5
6
6
6
6
6
5B/C
2
3
4
5
5
4-21
4