Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 44

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z16C35ISCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
transmission will be completed, but the remaining bits will
come from the SYNC registers rather than the remainder
of the CRC.
There are two modem control signals associated with the
transmitter provided by the ISCC: /RTS and /CTS.
The /RTS pin is a simple output that carries the inverted
state of the RTS bit (D1) in WR5.
The /CTS pin is ordinarily a simple input to the CTS bit in
RR0. However, if Auto Enables mode is selected this pin
becomes an enable for the transmitter. That is, if Auto En-
ables is ON and the /CTS pin is High the transmitter is dis-
abled. While the /CTS pin is Low, transmitter is enabled.
The initialization sequence for the transmitter in character-
oriented mode is shown in Table 4-6.
At this point, the other registers should be initialized as
necessary. When all of this is completed the transmitter
maybe enabled by setting bit 3 of WR5 to one. Now that
the transmitter is enabled the CRC generator maybe ini-
tialized by issuing the Reset Tx CRC Generator command
in WR0, bit 6-7.
4-10
Register Bit No
WR4
WR5
WR10
Table 4-6. Transmitter Initialization in
0,1
5,6
Character Oriented Mode
1
2
7
Description
select parity
RTS
select CRC generator
select number of bits per
character
CRC preset value
4.3.2 Byte-Oriented Synchronous Receive
The CPU places the receiver in Hunt mode whenever
transmission begins (or whenever a data dropout has oc-
curred and the hardware determines that resynchroniza-
tion is necessary). In Hunt mode, the receiver shifts a bit
into the Receive Shift register and compares the contents
of the Receive Shift register and with the sync character
(stored in another register), repeating the process until a
match occurs. When a match occurs, the receiver begins
transferring bytes to the receive FIFO.
Once the sync character-oriented mode has been select-
ed, any of the four sync character length maybe selected:
6-bits, 8-bits, 12-bits, or 16-bits.
The Table 4-7 shows the WR register bit setting for select-
ing sync character length.
The arrangement of the sync character in WR6 and WR7
is shown in Figure 4-5.
Sync Length
12 bits
16 bits
6 bits
8 bits
Table 4-7. Sync Character Length Selection
WR4,D5
0
0
0
0
WR4,D4
0
0
1
1
UM011001-0601
WR10,D0
1
0
1
0