DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 19

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

Updating the ANAR to suppress an ability is one way for a
management agent to change (restrict) the technology that
is used.
The
(ANLPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER) indi-
cates additional Auto-Negotiation status. The ANER pro-
vides status on:
— Whether or not a Parallel Detect Fault has occurred
— Whether or not the Link Partner supports the Next Page
— Whether or not the DP83849I supports the Next Page
— Whether or not the current page being exchanged by
— Whether or not the Link Partner supports Auto-Negotia-
2.1.3 Auto-Negotiation Parallel Detection
The DP83849I supports the Parallel Detection function as
defined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to moni-
tor the receive signal and report link status to the Auto-
Negotiation function. Auto-Negotiation uses this informa-
tion to configure the correct technology in the event that the
Link Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASE-
T PMAs recognize as valid link signals.
If the DP83849I completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may deter-
mine that negotiation completed via Parallel Detection by
reading a zero in the Link Partner Auto-Negotiation Able bit
once the Auto-Negotiation Complete bit is set. If configured
for parallel detect mode and any condition other than a sin-
gle good link occurs then the parallel detect fault bit will be
set.
2.1.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted
at any time by setting bit 9 (Restart Auto-Negotiation) of the
BMCR to one. If the mode configured by a successful Auto-
Negotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configu-
ration for the link. This function ensures that a valid config-
uration is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a manage-
ment agent, will cause the DP83849I to halt any transmit
data and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83849I
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.
function
function
Auto-Negotiation has been received
tion
Auto-Negotiation
will
resume
Link
Auto-Negotiation
Partner
Ability
after
Register
the
19
2.1.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83849I has been initial-
ized upon power-up as a non-auto-negotiating device
(forced technology), and it is then required that Auto-Nego-
tiation or re-Auto-Negotiation be initiated via software,
bit 12 (Auto-Negotiation Enable) of the Basic Mode Control
Register (BMCR) must first be cleared and then set for any
Auto-Negotiation function to take effect.
2.1.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to complete. In addition, Auto-Negotiation with
next page should take approximately 2-3 seconds to com-
plete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full
description of the individual timers related to Auto-Negotia-
tion.
2.2 Auto-MDIX
When enabled, this function utilizes Auto-Negotiation to
determine the proper configuration for transmission and
reception of data and subsequently selects the appropriate
MDI pair for MDI/MDIX operation. The function uses a ran-
dom seed to control switching of the crossover circuitry.
This implementation complies with the corresponding IEEE
802.3 Auto-Negotiation and Crossover Specifications.
Auto-MDIX is enabled by default and can be configured via
strap or via PHYCR (19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be
enabled in forcing crossover of the MDI pairs. Forced
crossover can be achieved through the FORCE_MDIX bit,
bit 14 of PHYCR (19h) register.
Note: Auto-MDIX will not work in a forced mode of opera-
tion.
2.3 PHY Address
The 4 PHY address inputs pins are shown below.
The DP83849I provides four address strap pins for deter-
mining the PHY addresses for ports A and B of the device.
The 4 address strap pins provide the upper four bits of the
PHY address. The lowest bit of the PHY address is depen-
dent on the port. Port A has a value of 0 for the PHY
address bit 0 while port B has a value of 1. The PHY
address strap input pins are shown in Table 2.
The PHY address strap information is latched into the
PHYCR register (address 19h, bits [4:0]) at device power-
up and hardware reset. The PHY Address pins are shared
with the RXD pins. Each DP83849I or port sharing an
Pin #
58
57
4
5
Table 2. PHY Address Mapping
PHYAD Function
PHYAD1
PHYAD2
PHYAD3
PHYAD4
RXD Function
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RXD0_A
RXD1_A
RXD0_B
RXD1_B