DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 31

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

3.6.3 Serial Management Preamble Suppression
The DP83849I supports a Preamble Suppression mode as
indicated by a one in bit 6 of the Basic Mode Status Regis-
ter (BMSR, address 01h.) If the station management entity
(i.e. MAC or other management controller) determines that
all PHYs in the system support Preamble Suppression by
returning a one in this bit, then the station management
entity need not generate preamble for each management
transaction.
The DP83849I requires a single initialization sequence of
32 bits of preamble following hardware/software reset. This
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or
the management access made to determine whether Pre-
amble Suppression is supported.
While the DP83849I requires an initial preamble sequence
of 32 bits for management initialization, it does not require
MDC
MDIO
(STA)
Z
Idle
Z
0
Start
1
Opcode
(Write)
0
1
0
(PHYAD = 0Ch)
PHY Address
1 1 0 0 0 0 0 0 0
Figure 6. Typical MDC/MDIO Write Operation
Register Address
(00h = BMCR)
31
1
TA
a full 32-bit sequence between each subsequent transac-
tion. A minimum of one idle bit between management
transactions is required as specified in the IEEE 802.3u
specification.
3.6.4 Simultaneous Register Write
The DP83849I incorporates a mode which allows simulta-
neous write access to both Port A and B register blocks at
the same time. This mode is selected by setting bit 15 of
RMII and Bypass Register (RBR, address 17h) in Port A.
As long as this bit remains set, subsequent writes to Port A
will write to registers in both ports.
Register reads are unaffected. Each port must still be read
individually.
0 0 0
0 0
0 0 0
Register Data
0
0 0 0 0 0 0 0 0
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Z
Idle
Z