DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 69

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

7.2.4 RMII and Bypass Register (RBR)
This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII, RMII, or Single
Clock MII mode for Receive or Transmit. In addition, several additional bits are included to allow datapath selection for
Transmit and Receive in multiport applications.
12:11
10:9
Bit
15
14
13
8
7
6
DIS_TX_OPT
TX_SOURCE
SIM_WRITE
PMD_LOOP
RESERVED
RX_PORT
SCMII_RX
SCMII_TX
Bit Name
Table 36. RMII and Bypass Register (RBR), addresses 17h
Strap, RW
Strap, RW
Strap, RW
Default
00, RW
0, RW
0, RW
0, RW
0, RO
Simultaneous Write:
Setting this bit in port A register space enables simultaneous write to Phy
registers in both ports. Subsequent writes to port A registers will write to
registers in both ports A and B.
1 = Simultaneous writes to both ports
0 = Per-port write
RESERVED: Writes ignored, Read as 0
Disable RMII TX Latency Optimization:
Normally the RMII Transmitter will minimize the transmit latency by
realigning the transmit clock with the Reference clock phase at the
start of a packet transmission. Setting this bit will disable Phase re-
alignment and ensure that IDLE bits will always be sent in multiples
of the symbol size. This will result in a larger uncertainty in RMII
transmit latency.
Receive Port:
See Section 3.5 for more information on Flexible Port Switching.
Transmit Source:
See Section 3.5 for more information on Flexible Port Switching.
00 = Not strapped for Extender Mode
10 = Strapped for Extender Mode
PMD Loopback:
0= Normal Operation
1= Remote (PMD) Loopback
Setting this bit will cause the device to Loopback data received
from the Physical Layer. The loopback is done prior to the MII or
RMII interface. Data received at the internal MII or RMII interface
will be applied to the transmitter. This mode should only be used if
RMII mode or Single Clock MII mode is enabled.
Single Clock RX MII Mode:
0= Standard MII mode
1= Single Clock RX MII Mode
Setting this bit will cause the device to generate receive data
(RX_DV, RX_ER, RXD[3:0]) synchronous to the X1 Reference
clock. RX_CLK is not used in this mode. This mode uses the RMII
elasticity buffer to tolerate variations in clock frequencies. This bit
cannot be set if RMII_MODE is set to a 1. This bit is strapped to 1
if EXTENDER_EN is 1 and RMII Mode is not strapped at hard re-
set.
Single Clock TX MII Mode:
0= Standard MII mode
1= Single Clock TX MII Mode
Setting this bit will cause the device to sample transmit data
(TX_EN, TXD[3:0]) synchronous to the X1 Reference clock.
TX_CLK is not used in this mode. This bit cannot be set if
RMII_MODE is set to a 1. This bit is strapped to 1 if
EXTENDER_EN is 1 and RMII Mode is not strapped at hard reset.
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Description
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