AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 248

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
Figure 17-2. FREEZE signal waveform
The application can check the ECC Status Registers (SR1/SR2) for any detected errors. It is up
to the application to correct any detected error for ECC-H. The application can correct any
detected error or let the hardware do the correction by writing a one to the Correction Enable bit
in the MD register (MD.CORRS4) for ECC-RS.
ECC computation can detect four different circumstances:
ECC Status Registers, ECC Parity Registers are cleared when a read/write command is
detected or a software reset is performed.
For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) Hsiao code is used.
24-bit ECC is generated in order to perform one bit correction per 256 or 512 bytes for pages of
512/2048/4096 8-bit words. 32-bit ECC is generated in order to perform one bit correction per
512/1024/2048/4096 8- or 16-bit words.They are generated according to the schemes shown in
Figure 17-3 on page 249
• No error: XOR between the ECC computation and the ECC code stored at the end of the
• Recoverable error: Only the Recoverable Error bits in the ECC Status registers
• ECC error: The ECC Error bits in the ECC Status Registers (SR1.ECCERRn /
• Non correctable error: The Multiple Error bits (MULERRn) in the SR1 and SR2 registers are
NAND Flash or SmartMedia
be cleared.
(SR1.RECERRn and/or SR2.RECERRn) are set. The corrupted word offset in the read page
is defined by the Word Address field (WORDADDR) in the PR0 to PR15 registers. The
corrupted bit position in the concerned word is defined in the Bit Address field (BITADDR) in
the PR0 to PR15 registers.
SR2.ECCERRn) are set. An error has been detected in the ECC code stored in the Flash
memory. The position of the corrupted bit can be found by the application performing an XOR
between the Parity and the NParity contained in the ECC code stored in the Flash memory.
For ECC-RS it is the responsibility of the software to determine where the error is located on
ECC code stored in the spare zone flash area and not on user data area.
set. Several unrecoverable errors have been detected in the Flash memory page.
FREEZE
512B
and
Figure 17-4 on page
™
page is equal to zero. All bits in the SR1 and SR2 registers will
512B
Nand Flash page 2048B
512B
250.
512B
Spare Zone
248