AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 804

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29. HSB Bus Performance Monitor (BUSMON)
29.1
29.2
29.3
32072G–11/2011
Features
Overview
Block Diagram
Rev 1.0.0.0
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•
•
BUSMON allows the user to measure the activity and stall cycles on the High Speed Bus (HSB).
Up to 4 device-specific masters can be measured. Each of these masters is part of a measure-
ment channel. Which masters that are connected to a channel is device-specific. Devices may
choose not to implement all channels.
Figure 29-1. BUSMON Block Diagram
Allows performance monitoring of High Speed Bus master interfaces
The following is monitored
Automatic handling of event overflow
– Up to 4 masters can be monitored
– Peripheral Bus access to monitor registers
– Data transfer cycles
– Bus stall cycles
– Maximum access latency for a single transfer
Master A
Master B
Master C
Master D
Master E
Master F
Master G
Master H
Master I
Master J
Master K
Master L
Master M
Master N
Master O
Master P
Channel 0
Channel 1
Channel 2
Channel 3
Registers
Registers
Registers
Registers
Control
Peripheral Bus Interface
Slave 0
Slave 1
Slave 2
Slave 3
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