AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 710

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.8.3
26.8.3.1
Register Name:
Access Type:
Offset:
Reset Value:
• SPDCONF: Speed Configuration
• RESUME: Send USB Resume
• RESET: Send USB Reset
• SOFE: Start of Frame Generation Enable
32072G–11/2011
31
23
15
7
-
-
-
-
This field contains the host speed capability.
Writing a one to this bit will generate a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
Writing a zero to this bit has no effect.
This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one).
Writing a one to this bit will generate a USB Reset on the USB bus.
This bit is cleared when the USB Reset has been sent.
It may be useful to write a zero to this bit when a device disconnection is detected (UHINT.DDISCI is one) whereas a USB Reset
is being sent.
Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep alive in low speed mode.
Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state.
This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.RXRSMI).
0
0
1
1
USB Host Registers
SPDCONF
Host General Control Register
30
22
14
6
-
-
-
-
UHCON
Read/Write
0x0400
0x00000000
0
1
0
1
29
21
13
5
-
-
-
Speed
Normal mode: the host start in full-speed mode and perform a high-speed reset to switch to
the high-speed mode if the downstream peripheral is high-speed capable.
reserved, do not use this configuration
reserved, do not use this configuration
Full-speed: the host remains to full-speed mode whatever is the peripheral speed capability.
SPDCONF
28
20
12
4
-
-
-
27
19
11
3
-
-
-
-
RESUME
26
18
10
2
-
-
-
RESET
25
17
9
1
-
-
-
SOFE
24
16
8
0
-
-
-
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