AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 577

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.9.9
25.6.9.10
Figure 25-43. Response Data Length
32072G–11/2011
Break
Sync
Node Action
LIN Response Data Length
Sync
Field
After an identifier transaction, a LIN response mode has to be selected. This is done in the Node
Action field (LINMR.NACT). Below are some response modes exemplified in a small LIN cluster:
The response data length is the number of data fields (bytes), excluding the checksum.
The response data length can be configured, either by the user, or automatically by bits 4 and 5
in the Identifier (IDCHR), in accordance to LIN 1.1. The user selects mode by writing to the Data
Length Mode bit (LINMR.DML):
• PARDIS=0: During header transmission, the parity bits are computed and in the shift register
• PARDIS=1: During header transmission, all the bits in IDCHR are sent on the bus. During
• Response, from master to slave1:
• Response, from slave1 to master:
• Response, from slave1 to slave2:
• DLM=0: the response data length is configured by the user by writing to the 8-bit Data Length
they replace bits six and seven from IDCHR. During header reception, the parity bits are
checked and can generate a LIN Identifier Parity Error (see
seven in IDCHR read as zero when receiving.
header reception, all the bits in IDCHR are updated with the received Identifier.
Control field (LINMR.DLC). The response data length equals DLC + 1 bytes.
Master: NACT=PUBLISH
Slave1: NACT=SUBSCRIBE
Slave2: NACT=IGNORE
Master: NACT=SUBSCRIBE
Slave1: NACT=PUBLISH
Slave2: NACT=IGNORE
Master: NACT=IGNORE
Slave1: NACT=PUBLISH
Slave2: NACT=SUBSCRIBE
Identifier
Field
Data
Field
User configuration: 1 - 256 data fields (DLC+1)
Identifier configuration: 2/4/8 data fields
Data
Field
Field
Data
Section
25.6.10). Bits six and
Data
Field
Checksum
Field
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