AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 60

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6.4
Name:
Access Type:
Offset:
Reset Value:
• PLLTEST: PLL Test
• PLLCOUNT: PLL Count
• PLLMUL: PLL Multiply Factor
• PLLDIV: PLL Division Factor
• PLLOPT: PLL Option
• PLLOSC: PLL Oscillator Select
32072G–11/2011
PLLOPT[0]: VCO frequency
PLLOPT[1]: Output divider
PLLOPT[2]
PLLTEST
31
23
15
7
-
-
-
Reserved for internal use. Always write to 0.
Specifies the number of slow clock cycles before ISR.LOCKn will be set after PLLn has been written, or after PLLn has been
automatically re-enabled after exiting a sleep mode.
These fields determine the ratio of the PLL output frequency to the source oscillator frequency. Formula is detallied in
7.5.4.1
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range
PLLOPT[1]: Enable the extra output divider
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time)
0: Oscillator 0 is the source for the PLL.
1: Oscillator 1 is the source for the PLL.
PLL Control Registers
30
22
14
PLL0,1
Read/Write
0x20-0x24
0x00000000
6
-
-
-
-
0
1
0
1
0
1
29
21
13
5
-
-
-
Description
160MHz<f
80MHz<f
f
f
Wide Bandwidth Mode enabled
Wide Bandwidth Mode disabled
PLL
PLL
= f
= f
vco
vco
vco
/2
vco
<180MHz
<240MHz
28
20
12
4
-
-
PLLOPT
27
19
11
3
PLLCOUNT
26
18
10
2
PLLMUL
PLLDIV
PLLOSC
25
17
9
1
PLLEN
24
16
Section
8
0
60