AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 366

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.12.13 Interrupt Mask Registers
Name:
Access Type:
Offset:
Reset Value:
The contents of the Raw Status Registers are masked with the contents of the Mask Registers: MaskTfr, MaskBlock, Mask-
SrcTran, MaskDstTran, MaskErr. Each Interrupt Mask register has a bit allocated per channel, for example, MaskTfr[2] is
the mask bit for Channel 2’s transfer complete interrupt.
A channel’s INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted
on the same System Bus write transfer. This allows software to set a mask bit without performing a read-modified write
operation.
For example, writing hex 01x1 to the MaskTfr register writes a 1 into MaskTfr[0], while MaskTfr[7:1] remains unchanged.
Writing hex 00xx leaves MaskTfr[7:0] unchanged.
Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMACA to set the appropri-
ate bit in the Status Registers.
• INT_M_WE[11:8]: Interrupt Mask Write Enable
• INT_MASK[3:0]: Interrupt Mask
32072G–11/2011
31
23
15
7
-
-
-
-
0 = Write disabled
1 = Write enabled
0= Masked
1 = Unmasked
30
22
14
6
-
-
-
-
MaskTfr, MaskBlock, MaskSrcTran, MaskDstTran, MaskErr
Read/Write
0x310, 0x318, 0x320, 0x328, 0x330
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
INT_M_WE3
INT_MASK3
27
19
11
3
-
-
INT_M_WE2
INT_MASK2
26
18
10
2
-
-
INT_M_WE1
INT_MASK1
25
17
9
1
-
-
INT_M_WE0
INT_MASK0
24
16
8
0
-
-
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