ATmega169P Atmel Corporation, ATmega169P Datasheet - Page 126

• Manufacturer Part Number: ATmega169P
• Manufacturer: Atmel Corporation

Specifications of ATmega169P

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.10 Timer/Counter Timing Diagrams
8018P–AVR–08/10
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase and frequency correct PWM mode. If the OCR1x is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be set to
high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic val-
ues. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A
output will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 15-11
Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Figure 15-12 on page 127
using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM.
The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
TCNTn
OCRnx
OCFnx
TCNTn
OCRnx
(clk
OCFnx
(clk
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
shows the same timing data, but with the prescaler enabled.
OCRnx - 1
OCRnx - 1
shows the count sequence close to TOP in various modes. When
Figure 15-10
OCRnx
OCRnx
OCRnx Value
OCRnx Value
shows a timing diagram for the setting of OCF1x.
OCRnx + 1
OCRnx + 1
T1
ATmega169P
) is therefore shown as a
OCRnx + 2
OCRnx + 2
clk_I/O
/8)
126