ATmega169P Atmel Corporation, ATmega169P Datasheet - Page 172

• Manufacturer Part Number: ATmega169P
• Manufacturer: Atmel Corporation

Specifications of ATmega169P

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.3.2
19.3.3
8018P–AVR–08/10
Double Speed Operation (U2Xn)
External Clock
Table 19-1.
Note:
Some examples of UBRRn values for some system clock frequencies are found in
page
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCK clock frequency
is limited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
Operating Mode
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn = 1)
Synchronous Master
mode
190.
BAUD
f
UBRRn
OSC
1. The baud rate is defined to be the transfer rate in bit per second (bps)
osc
depends on the stability of the system clock source. It is therefore recommended to
Equations for Calculating Baud Rate Register Setting
Figure 19-2 on page 171
Baud rate (in bits per second, bps).
System Oscillator clock frequency.
Contents of the UBRRHn and UBRRLn Registers, (0-4095).
Equation for Calculating Baud
BAUD
BAUD
BAUD
=
=
=
Rate
----------------------------------------- -
16 UBRRn
f
for details.
-------------------------------------- -
2 UBRRn
-------------------------------------- -
8 UBRRn
XCK
(
(
(
(1)
f
<
f
f
OSC
OSC
OSC
f
---------- -
OSC
4
+
+
+
1
1
1
)
)
)
Equation for Calculating UBRRn
UBRRn
UBRRn
UBRRn
ATmega169P
=
=
=
Value
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
OSC
OSC
OSC
Table 19-4 on
–
–
–
172