ATmega169P Atmel Corporation, ATmega169P Datasheet - Page 235

• Manufacturer Part Number: ATmega169P
• Manufacturer: Atmel Corporation

Specifications of ATmega169P

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.2.2
23.2.3
23.2.4
8018P–AVR–08/10
LCD Clock Sources
LCD Prescaler
LCD Memory
Figure 23-1. LCD Module Block Diagram
The LCD Controller can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
LCDCS bit in the LCDCRB Register is written to logic one, the clock source is taken from the
TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC voltage
offset across LCD segments.
The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The LCDPS2:0 bits
selects clk
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock further by
1 to 8.
Output from the clock divider clk
The display memory is available through I/O Registers grouped for each common terminal.
When a bit in the display memory is written to one, the corresponding segment is energized (on),
and non-energized when a bit in the display memory is written to zero.
D
A
T
A
B
U
S
LCD
divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
LCDCCR
LCDFRR
LCDCRA
LCDCRB
TOSC
LCDDR 18 -15
LCDDR 13 -10
clk
LCDDR 8 - 5
LCDDR 3 - 0
i/o
lcdcc3:0
0
1
lcdcs
Configuration
LATCH
array
Display
LCD_PS
clk
LCD
Contrast Controller/
LCD
Power Supply
lcdps2:0
lcdcd2:0
is used as clock source for the LCD timing.
is by default equal to the system clock, clk
MUX
25 x
4:1
Divide by 1 to 8
12-bit Prescaler
LCD_voltage_ok
Multiplexer
LCD Ouput
Decoder
Timing
Clock
LCD
clk
LCD_PS
LCD Buffer/
Driver
CAP
LCD
1/3 V
1/2 V
2/3 V
V
LCD
LCD
LCD
LCD
ATmega169P
Analog
Switch
Array
I/O
. When the
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
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