SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 203

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

10.22.5
• XN
Instruction access disable bit:
0 = instruction fetches enabled
1 = instruction fetches disabled.
• AP
Access permission field, see
• TEX, C, B
Memory access attributes, see
• S
Shareable bit, see
• SRD
Subregion disable bits. For each bit in this field:
0 = corresponding sub-region is enabled
1 = corresponding sub-region is disabled
See
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD
field as 0x00.
• SIZE
Specifies the size of the MPU protection region. The minimum permitted value is 3 (b00010), see See
on page 204
• ENABLE
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
“Subregions” on page 208
31
23
15
7
MPU Region Attribute and Size Register
Reserved
Reserved
for more information.
Reserved
Table 10-36 on page
30
22
14
6
The RASR defines the region size and memory attributes of the MPU region specified by the
RNR, and enables that region and any subregions. See the register summary in
page 197
RASR is accessible using word or halfword accesses:
The bit assignments are:
• the most significant halfword holds the region attributes
• the least significant halfword holds the region size and the region and subregion enable bits.
Table 10-39 on page
Table 10-37 on page
for more information.
for its attributes.
29
21
13
5
204.
205.
TEX
XN
28
20
12
204.
4
SRD
Reserved
SIZE
27
19
11
3
26
18
10
S
2
SAM3S8/SD8
SAM3S8/SD8
AP
25
17
C
9
1
“SIZE field values”
Table 10-35 on
ENABLE
24
16
B
8
0
203
203