SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 902

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

35.6.5.5
902
902
SAM3S8/SD8
SAM3S8/SD8
Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the
channel 0 is enabled (see
To prevent unexpected comparison match, the user must use the
Update Register”
and PWM_CMPMUPDx) to change respectively the comparison values and the comparison
configurations while the channel 0 is still enabled. These registers hold the new values until the
end of the comparison update period (when CUPRCNT is equal to CUPR in
x Mode Register”
ues for the next period.
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be fol-
lowed by a write of the register PWM_CMPMUPDx.
Note:
Figure 35-19. Synchronized Update of Comparison Values and Configurations
If the update registers PWM_CMPVUPDx and PWM_CMPMUPDx are written several times
between two updates, only the last written value are taken into account.
End of channel0 PWM period and
end of Comparison Update Period and
and PWM_CMPMx written
End of channel0 PWM period and
end of Comparison Update Period
(PWM_CMPMx) and the end of the current PWM period, then update the val-
and the
Section 35.6.3 “PWM Comparison
“PWM Comparison x Mode Update Register”
PWM_CMPVUPDx Value
Comparison Value
for comparison x
PWM_CMPVx
User's Writing
Units”).
PWM_CMPMUPDx Value
Comparison configuration
“PWM Comparison x Value
for comparison x
User's Writing
PWM_CMPMx
(PWM_CMPVUPDx
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
“PWM Comparison