SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 386

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

23.8.3
23.8.3.1
23.8.3.2
Figure 23-9. Write Cycle
386
386
SAM3S8/SD8
SAM3S8/SD8
Write Waveforms
NWE Waveforms
NCS Waveforms
A [23:0]
NWE
MCK
NCS
The write protocol is similar to the read protocol. It is depicted in
starts with the address setting on the memory address bus.
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined:
1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before
2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE
3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after
1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before
2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and
3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the
NCS_WR_SETUP
the NWE falling edge;
rising edge;
the NWE rising edge.
the NCS falling edge.
NCS rising edge;
NCS rising edge.
NWE_SETUP
NCS_WR_PULSE
NWE_PULSE
NWE_CYCLE
NWE_HOLD
NCS_WR_HOLD
Figure
23-9. The write cycle
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12