SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 383

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

23.8.1.4
Figure 23-6. No Setup, No Hold on NRD and NCS Read Signals
23.8.1.5
23.8.2
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Read Mode
Null Delay Setup and Hold
Null Pulse
A[23:0]
D[7:0]
MCK
NRD
NCS
All NRD and NCS timings are defined separately for each chip select as an integer number of
Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define
the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time
and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain
active continuously in case of consecutive read cycles in the same memory (see
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
ings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register
of the corresponding chip select indicates which signal of NRD and NCS controls the read
operation.
NCS_RD_PULSE
NRD_PULSE
NRD_CYCLE
NCS_RD_PULSE
NRD_PULSE
NRD_CYCLE
NCS_RD_PULSE
NRD_PULSE
NRD_CYCLE
SAM3S8/SD8
SAM3S8/SD8
Figure
23-6).
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