SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 397

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

Figure 23-19. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins
23.11.3
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
NCS0
D[7:0]
NWE
MCK
NRD
TDF Optimization Disabled (TDF_MODE = 0)
read access on NCS0 (NRD controlled)
When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that
the data float period is ended when the second access begins. If the hold period of the read1
controlling signal overlaps the data float period, no additional tdf wait states will be inserted.
Figure
with no TDF optimization.
• read access followed by a read access on another chip select,
• read access followed by a write access on another chip select,
• read access followed by a write access on the same chip select,
23-20,
NRD_HOLD= 4
Figure 23-21
TDF_CYCLES = 6
and
Read to Write
Wait State
Figure 23-22
NWE_SETUP= 3
write access on NCS0 (NWE controlled)
illustrate the cases:
SAM3S8/SD8
SAM3S8/SD8
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