LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 28

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 14.
LPC2926_27_29
Product data sheet
Pin name
USB_VBUS
USB_D+
USB_D−
USB_CONNECT
USB_UP_LED
USB_SCL
USB_SDA
USB_LS
USB_RST
USB_INT
USB_SSPND
USB OTG port pins
6.11.3 Pin description
6.11.4 Clock description
Direction
I
I/O
I/O
O
O
I/O
I/O
O
O
O
O
The USB OTG controller has the following features:
Access to the USB registers is clocked by the CLK_SYS_USB, derived from
BASE_SYS_CLK, see
the USB block, BASE_USB_CLK and BASE_USB_I2C_CLK (see
•
•
•
•
Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
Hardware support for Host Negotiation Protocol (HNP).
Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
Description
V
via its corresponding PINSEL register, it is driven
HIGH internally.
Positive differential data
Negative differential data
SoftConnect control signal
GoodLink LED control signal
I
I
Low speed status (applies to host functionality only)
USB reset status
USB transceiver interrupt
Bus suspend status
2
2
BUS
C serial clock
C serial data
status input. When this function is not enabled
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
Section
6.7.2. The CGU1 provides two independent base clocks to
ARM9 microcontroller with CAN, LIN, and USB
LPC2926/2927/2929
Connection
USB Connector
USB Connector
USB Connector
Control
Control
External OTG transceiver
External OTG transceiver
External OTG transceiver
External OTG transceiver
External OTG transceiver
External OTG transceiver
Section
© NXP B.V. 2010. All rights reserved.
6.16.3).
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