LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 4

The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2

LPC2926_27_29

Manufacturer Part Number
LPC2926_27_29
Description
The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
4. Block diagram
LPC2926_27_29
Product data sheet
Fig 1.
TIMER0/1 MTMR
LPC2926/2927/2929
ACCEPTANCE
QUADRATURE
MANAGEMENT
3.3 V ADC1/2
UART/LIN0/1
Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA.
PWM0/1/2/3
LPC2926/2927/2929 block diagram
GENERATION
GENERATION
ENCODER
5 V ADC0
GLOBAL
FILTER
CAN0/1
I2C0/1
POWER
CLOCK
RESET
UNIT
UNIT
UNIT
CONTROLLER
INTERRUPT
VECTORED
networking subsystem
power. clock, and
reset subsystem
MSC subsystem
AHB TO DTL
AHB TO APB
AHB TO APB
AHB TO DTL
BRIDGE
BRIDGE
BRIDGE
BRIDGE
All information provided in this document is subject to legal disclaimers.
1 master
ITCM
32 kB
2 slaves
Rev. 5 — 28 September 2010
slave
slave
slave
slave
TEST/DEBUG
ARM968E-S
INTERFACE
8 kB SRAM
interface
JTAG
MATRIX
MULTI-
LAYER
AHB
master
master
master
slave
slave
slave
slave
slave
slave
slave
slave
DTCM
32 kB
ARM9 microcontroller with CAN, LIN, and USB
peripheral subsystem
general subsystem
EMBEDDED SRAM 16 kB
EMBEDDED SRAM 32 kB
MEMORY CONTROLLER
AHB TO APB
AHB TO APB
GPDMA CONTROLLER
GPDMA REGISTERS
EMBEDDED FLASH
BRIDGE
BRIDGE
EXTERNAL STATIC
USB OTG/DEVICE
CONTROLLER
LPC2926/2927/2929
512/768 kB
SYSTEM CONTROL
GENERAL PURPOSE I/O
CHIP FEATURE ID
EVENT ROUTER
EEPROM
16 kB
PORTS 0/1/2/3/5
RS485 UART0/1
TIMER 0/1/2/3
© NXP B.V. 2010. All rights reserved.
SPI0/1/2
WDT
002aae143
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