LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 32

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
6.13.3.1 Pin description
6.13.3.2 Clock description
The timers are designed to count cycles of the clock and optionally generate interrupts or
perform other actions at specified timer values, based on four match registers. They also
include capture inputs to trap the timer value when an input signal changes state,
optionally generating an interrupt. The core function of the timers consists of a 32 bit
prescale counter triggering the 32 bit timer counter. Both counters run on clock
CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this
clock. Note that each timer has its individual clock source within the Peripheral
SubSystem. In the Modulation and Sampling SubSystem each timer also has its own
individual clock source. See
The four timers in the peripheral subsystem of the LPC2926/2927/2929 have the pins
described below. The two timers in the modulation and sampling subsystem have no
external pins except for the pause pin on MSCSS timer 1. See
description of these timers and their associated pins. The timer pins are combined with
other functions on the port pins of the LPC2926/2927/2929, see
shows the timer pins (x runs from 0 to 3).
Table 16.
Note that CAP0 and CAP1 are not pinned out on Timer1.
The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx
(x = 0 to 3), see
for power management. The frequency of all these clocks is identical as they are derived
from the same base clock BASE_CLK_TMR. The register interface towards the system
bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by
CLK_TMRx.
Symbol
TIMERx CAP[0]
TIMERx CAP[1]
TIMERx CAP[2]
TIMERx CAP[3]
TIMERx MAT[0]
TIMERx MAT[1]
TIMERx MAT[2]
TIMERx MAT[3]
•
•
Up to four external outputs per timer corresponding to match registers, with the
following capabilities:
– Set LOW on match
– Set HIGH on match
– Toggle on match
– Do nothing on match
Pause input pin (MSCSS timers only)
Timer pins
All information provided in this document is subject to legal disclaimers.
Section
Pin name
CAPx[0]
CAPx[1]
CAPx[2]
CAPx[3]
MATx[0]
MATx[1]
MATx[2]
MATx[3]
Rev. 5 — 28 September 2010
6.7.2. Note that each timer has its own CLK_TMRx branch clock
Section 6.16.5
OUT
OUT
OUT
OUT
Direction
IN
IN
IN
IN
ARM9 microcontroller with CAN, LIN, and USB
for information on generation of these clocks.
LPC2926/2927/2929
Description
TIMER x capture input 0
TIMER x capture input 1
TIMER x capture input 2
TIMER x capture input 3
TIMER x match output 0
TIMER x match output 1
TIMER x match output 2
TIMER x match output 3
Section 6.15.6
Section
© NXP B.V. 2010. All rights reserved.
6.12.3.
for a
Table 16
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